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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16301-2E
32-bit RISC Microcontroller
CMOS
FR30 Series
MB91101/MB91101A
s DESCRIPTION
The MB91101 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91101 normally operates in the external bus access mode and executes instructions on the internal 1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance. The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers. *: FR Family stands for FUJITSU RISC controller.
s FEATURES
FR CPU 32-bit RISC, load/store architecture, 5-stage pipeline Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) General purpose registers: 32 bits x 16 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages * Register interlock functions, efficient assembly language coding * Branch instructions with delay slots: Reduced overhead time in branch executions * * * * * *
(Continued)
s PACKAGE
100-pin Plastic LQFP 100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
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MB91101/MB91101A
(Continued) * Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles * Interrupt (push PC and PS): 6 cycles, 16 priority levels
External bus interface Clock doubler: Internal 50 MHz, external bus 25 MHz operation 25-bit address bus (32 Mbytes memory space) 8/16-bit data bus Basic external bus cycle: 2 clock cycles Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6 Interface supported for various memory technologies DRAM interface (area 4 and 5) * Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area * Unused data/address pins can be configured us input/output ports * Little endian mode supported (Select 1 area from area 1 to 5) DRAM interface 2 banks independent control (area 4 and 5) Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode * Supports 8/9/10/12-bit column address width * 2CAS/1WE, 2WE/1CAS selective Cache memory * * * * * * * * * * * * * * * * * 1-Kbyte instruction cache memory 32 block/way, 4 entry(4 word)/block 2 way set associative Lock function: For specific program code to be resident in cashe memory 8 channels Transfer incident/external pins/internal resource interrupt requests Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer Transfer data length: 8 bits/16 bits/32 bits selective NMI/interrupt request enables temporary stop operation 3 independent channels Full-duplex double buffer Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) Asynchronous (start-stop system), CLK-synchronized communication selective Multi-processor mode Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate Use external clock can be used as a transfer clock Error detection: Parity, frame, overrun * * * * * * * * * * *
DMA controller (DMAC)
UART
2
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MB91101/MB91101A
(Continued)
10-bit A/D converter (successive approximation conversion type) * * * * * 10-bit resolution, 4 channels Successive approximation type: Conversion time of 5.6 s at 25 MHz Internal sample and hold circuit Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective Start: Software/external trigger/internal timer selective
16-bit reload timer * 3 channels * Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective Other interval timers * 16-bit timer: 3 channels (U-TIMER) * PWM timer: 4 channels * Watchdog timer: 1 channel Bit search module First bit transition "1" or "0" from MSB can be detected in 1 cycle Interrupt controller * External interrupt input: Non-maskable interrupt (NMI), normal interrupt x 4 (INT0 to INT3) * Internal interrupt incident: UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt module * Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) Others * Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset * Low-power consumption mode: Sleep mode/stop mode * Clock control Gear function: Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) However, operating frequency for peripherals is less than 25 MHz. * Packages: LQFP-100 and QFP-100 * CMOS technology (0.35 m) * Power supply voltage 5 V: CPU power supply 5.0 V 10% (internal regulator) A/D power supply 2.7 V to 3.6 V 3 V: CPU power supply 2.7 V to 3.6 V (without internal regulator) A/D power supply 2.7 V to 3.6 V
3
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MB91101/MB91101A
s PIN ASSIGNMENT
(Top view)
RAS1/PB4/EOP2 DW0/PB3 CS0H/PB2 CS0L/PB1 RAS0/PB0 INT0/PE0 INT1/PE1 VCC5 X0 X1 VSS INT2/SC1/PE2 INT3/SC2/PE3 DREQ0/PE4 DREQ1/PE5 DACK0/PE6 DACK1/PE7 OCPA0/PF7/ATG SO2/OCPA2/PF6 SI2/OCPA1/PF5 SO1/TRG3/PF4 SI1/TRG2/PF3 SC0/OCPA3/PF2 SO0/TRG1/PF1 SI0/TRG0/PF0 CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1/PB7 VCC3 CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3/EOP1 CS2/PA2 CS1/PA1 CS0 NMI HST RST VSS MD0 MD1 MD2 RDY/P80 BGRNT/P81 BRQ/P82 RD WR0 WR1/P85 D16/P20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
4
D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24 D25 D26 D27 D28 D29 D30 VSS D31 A00 VCC5 A01 A02 A03 A04 A05 A06 A07
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/EOP0 A23/P67 A22/P66 VSS A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 A16/P60 A15 A14 A13 A12 A11 A10 A09 A08
(FPT-100P-M05)
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MB91101/MB91101A
(Top view)
CS0L/PB1 RAS0/PB0 INT0/PE0 INT1/PE1 VCC5 X0 X1 VSS INT2/SC1/PE2 INT3/SC2/PE3 DREQ0/PE4 DREQ1/PE5 DACK0/PE6 DACK1/PE7 OCPA0/PF7/ATG SO2/OCPA2/PF6 SI2/OCPA1/PF5 SO1/TRG3/PF4 SI1/TRG2/PF3 SC0/OCPA3/PF2 CS0H/PB2 DW0/PB3 RAS1/PB4/EOP2 CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1/PB7 VCC3 CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3/EOP1 CS2/PA2 CS1/PA1 CS0 NMI HST RST VSS MD0 MD1 MD2 RDY/P80 BGRNT/P81 BRQ/P82 RD WR0 WR1/P85 D16/P20 D17/P21 D18/P22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SO0/TRG1/PF1 SI0/TRG0/PF0 AN3 AN2 AN1 AN0 AVSS/AVRL AVRH AVCC A24/EOP0 A23/P67 A22/P66 VSS A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 A16/P60 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05
D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24 D25 D26 D27 D28 D29 D30 VSS D31 A00 VCC5 A01 A02 A03 A04
(FPT-100P-M06)
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MB91101/MB91101A
s PIN DESCRIPTION
Pin no. LQFP*1 25 to 32 QFP*2 Pin name Circuit type C Function Bit 16 to bit 23 of external data bus Can be configured as I/O ports when external data bus width is set to 8-bit. C F F Bit 24 to bit 31 of external data bus Bit 00 to bit 15 of external address bus Bit 16 to bit 23 of external address bus
28 to 35 D16 to D23 P20 to P27
33 to 39, 41 42, 44 to 58 59 to 64, 66, 67
36 to 42, D24 to D30, 44 D31 45, A00, 47 to 61 A01 to A15 62 to 67, A16 to A21, 69, A22, 70 A23 P60 to P65, P66, P67
Can be configured as I/O ports when not used as address bus.
68
71
A24 EOP0
L
Bit 24 of external address bus Can be configured as DMAC EOP output (ch. 0) when DMAC EOP output is enabled.
19
22
RDY
C
External ready input Inputs "0" when bus cycle is being executed and not completed. Can be configured as a port when RDY is not used. External bus release acknowledge output Outputs "L" level when external bus is released. Can be configured as a port when BGRNT is not used. External bus release request input Inputs "1" when release of external bus is required. Can be configured as a port when BRQ is not used. Read strobe output pin for external bus Write strobe output pin for external bus Relation between control signals and effective byte locations is as follows: 16-bit bus width D15 to D08 WR0 WR1 8-bit bus width WR0 (I/O port enabled)
P80 20 23 BGRNT P81 21 24 BRQ P82 22 23 25 26 RD WR0 L L C F
24
27
WR1
F
D07 to D00
Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister when using at 16-bit bus width. P85 *1: FPT-100P-M05 *2: FPT-100P-M06 Can be configured as a port when WR1 is not used.
(Continued)
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MB91101/MB91101A
Pin no. LQFP* 11 10 9 8
1
QFP* 14 13 12 11
2
Pin name CS0 CS1 PA1 CS2 PA2 CS3 PA3 EOP1
Circuit type L F F F
Function Chip select 0 output ("L" active) Chip select 1 output ("L" active) Can be configured as a port when CS1 is not used. Chip select 2 output ("L" active) Can be configured as a port when CS2 is not used. Chip select 3 output ("L" active) Can be configured as a port when CS3 and EOP1 are not used. EOP output pin for DMAC (ch. 1) This function is available when EOP output for DMAC is enabled.
7 6 5
10 9 8
CS4 PA4 CS5 PA5 CLK PA6
F F F
Chip select 4 output ("L" active) Can be configured as a port when CS4 is not used. Chip select 5 output ("L" active) Can be configured as a port when CS5 is not used. System clock output Outputs clock signal of external bus operating frequency. Can be configured as a port when CLK is not used. RAS output for DRAM bank 0 Refer to the DRAM interface for details. Can be configured as a port when RAS0 is not used. CASL output for DRAM bank 0 Refer to the DRAM interface for details. Can be configured as a port when CS0L is not used. CASH output for DRAM bank 0 Refer to the DRAM interface for details. Can be configured as a port when CS0H is not used. WE output for DRAM bank 0 ("L" active) Refer to the DRAM interface for details. Can be configured as a port when DW0 is not used. RAS output for DRAM bank 1 Refer to the DRAM interface for details. Can be configured as a port when RAS1 and EOP2 are not used. DMAC EOP output (ch. 2) This function is available when DMAC EOP output is enabled.
96
99
RAS0 PB0
F
97
100
CS0L PB1
F
98
1
CS0H PB2
F
99
2
DW0 PB3
F
100
3
RAS1 PB4 EOP2
F
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
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MB91101/MB91101A
Pin no. LQFP* 1
1
QFP* 4
2
Pin name CS1L PB5 DREQ2
Circuit type F
Function CASL output for DRAM bank 1 Refer to the DRAM interface for details. Can be configured as a port when CS1L and DREQ2 are not used. External transfer request input pin for DMA This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
2
5
CS1H PB6 DACK2
F
CASH output for DRAM bank 1 Refer to the DRAM interface for details. Can be configured as a port when CS1H and DACK2 are not used. External transfer request acknowledge output pin for DMAC (ch. 2) This function is available when transfer request output for DMAC is enabled.
3
6
DW1 PB7
F
WE output for DRAM bank 1 ("L" active) Refer to the DRAM interface for details. Can be configured as a port when DW1 is not used. Mode pins 0 to 2 MCU basic operation mode is set by these pins. Directly connect these pins with VCC or VSS for use. Clock (oscillator) input Clock (oscillator) output External reset input Hardware standby input ("L" active) NMI (non-maskable interrupt pin) input ("L" active) External interrupt request input pins These pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. Can be configured as a I/O port when INT0, INT1 are not used.
16 to 18
19 to 21 MD0 to MD2
G
92 91 14 13 12 95, 94
95 94 17 16 15 98, 97
X0 X1 RST HST NMI INT0, INT1
A A B H H F
PE0, PE1 89 92 INT2 F
External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Clock I/O pin for UART1 Clock output is available when clock output of UART1 is enabled. Can be configured as a I/O port when INT2 and SC1 are not used. This function is available when UART1 clock output is disabled.
SC1 PE2
*1: FPT-100P-M05 *2: FPT-100P-M06 8
(Continued)
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MB91101/MB91101A
Pin no. LQFP* 88
1
QFP* 91
2
Pin name INT3
Circuit type F
Function External interrupt request input pin This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. UART2 clock I/O pin Clock output is available when UART2 clock output is enabled. Can be configured as a I/O port when INT3 and SC2 are not used. This function is available when UART2 clock output is disabled.
SC2 PE3 87, 86 90, 89 DREQ0, DREQ1 F
External transfer request input pins for DMA These pins are used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. Can be configured as a I/O port when DREQ0, DREQ1 are not used.
PE4, PE5 85 88 DACK0 F
External transfer request acknowledge output pin for DMAC (ch. 0) This function is available when transfer request output for DMAC is enabled. Can be configured as a I/O port when DACK0 is not used. This function is available when transfer request acknowledge output for DMAC or DACK0 output is disabled.
PE6
84
87
DACK1
F
External transfer request acknowledge output pin for DMAC (ch. 1) This function is available when transfer request output for DMAC is enabled. Can be configured as a I/O port when DACK1 is not used. This function is available when transfer request output for DMAC or DACK1 output is disabled.
PE7
76
79
SI0
F
UART0 data input pin This pin is used for input during UART0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PWM timer external trigger input pin This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Can be configured as a I/O port when SI0 and TRG0 are not used.
TRG0
PF0 *1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
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MB91101/MB91101A
Pin no. LQFP* 77
1
QFP* 80
2
Pin name SO0 TRG1
Circuit type F
Function UART0 data output pin This function is available when UART0 data output is enabled. PWM timer external trigger input pin This function is available when serial data output of PF1, UART0 are disabled. Can be configured as a I/O port when SO0 and TRG1 are not used. This function is available when serial data output of UART0 is disabled.
PF1
78
81
SC0 OCPA3 PF2
F
UART0 clock I/O pin Clock output is available when UART0 clock output is enabled. PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as a I/O port when SC0 and OCPA3 are not used. This function is available when UART0 clock output is disabled.
79
82
SI1
F
UART1 data input pin This pin is used for input during UART1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PWM timer external trigger input pin This pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Can be configured as a I/O port when SI1 and TRG2 are not used.
TRG2
PF3 80 83 SO1 TRG3 F
UART1 data output pin This function is available when UART1 data output is enabled. PWM timer external trigger input pin This function is available when PF4, UART1 data outputs are disabled. Can be configured as a I/O port when SO1 and TRG3 are not used. This function is available when UART1 data output is disabled.
PF4
81
84
SI2
F
UART2 data input pin This pin is used for input during UART2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as a I/O port when SI2 and OCPA1 are not used.
OCPA1 PF5 *1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
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MB91101/MB91101A
(Continued)
Pin no. LQFP* 82
1
QFP* 85
2
Pin name SO2 OCPA2 PF6
Circuit type F
Function UART2 data output pin This function is available when UART2 data output is enabled. PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as a I/O port when SO2 and OCPA2 are not used. This function is available when UART2 data output is disabled.
83
86
OCPA0 PF7
F
PWM timer output pin This function is available when PWM timer output is enabled. Can be configured as a I/O port when OCPA0 and ATG are not used. This function is available when PWM timer output is disabled. External trigger input pin for A/D converter This pin is used for input when external trigger is selected to cause A/D converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.
ATG
72 to 75
75 to 78 AN0 to AN3
D
Analog input pins of A/D converter This function is available when AIC register is set to specify analog input mode. Power supply pin (VCC) for A/D converter Reference voltage input (high) for A/D converter Make sure to turn on and off this pin with potential of AVRH or more applied to VCC. Power supply pin (VSS) for A/D converter and reference voltage input pin (low) 5 V power supply pin (VCC) for digital circuit Always two pins must be connected to the power supply (connect to 3 V power supply when operating at 3 V). Bypass capacitor pin for internal capacitor. Also connect this pin to 3 V power supply when operating at 3 V. Earth level (VSS) for digital circuit
69 70
72 73
AVCC AVRH
-- --
71 43, 93 4
74 46, 96 7
AVSS / AVRL VCC5
-- --
VCC3
--
15, 40, 65, 90
18, 43, 68, 93
VSS
--
*1: FPT-100P-M05 *2: FPT-100P-M06 Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. P82 and BRQ. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O.
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MB91101/MB91101A
s DRAM CONTROL PIN
Pin name RAS0 RAS1 CS0L CS0H CS1L CS1H CW0 DW1 Data bus 16-bit mode 2CAS/1WR mode Area 4 RAS Area 5 RAS Area 4 CASL Area 4 CASH Area 5 CASL Area 5 CASH Area 4 WE Area 5 WE 1CAS/2WR mode Area 4 RAS Area 5 RAS Area 4 CAS Area 4 WEL Area 5 CAS Area 5 WEL Area 4 WEH Area 5 WEH Data bus 8-bit mode -- Area 4 RAS Area 5 RAS Area 4 CAS Area 4 CAS Area 5 CAS Area 5 CAS Area 4 WE Area 5 WE Remarks Correspondence of "L" "H" to lower address 1 bit (A0) in data bus 16bit mode "L": "0" "H": "1" CASL: CAS which A0 corresponds to "0" area CASH: CAS which A0 corresponds to "1" area WEL: WE which A0 corresponds to "0" area WEH: WE which A0 corresponds to "1" area
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MB91101/MB91101A
s I/O CIRCUIT TYPE
Type A
X1 Clock input
Circuit
Remarks * Oscillation feedback resistance 1 M approx. With standby control
X0
Standby control signal
B
VCC P-ch P-ch
* CMOS level Hysteresis input Without standby control With pull-up resistance
R VSS
N-ch
Digital input
C
* CMOS level I/O With standby control
P-ch Digital output
R
N-ch
Digital output
Digital input Standby control signal
D
* Analog input
P-ch
Digital output
R
N-ch
Digital output
Analog input
(Continued)
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MB91101/MB91101A
Type E
Circuit
Remarks * N-ch open-drain output * CMOS level input With standby control
Digital output
P-ch
R
N-ch
Digital input Standby control signal
F
P-ch Digital output
* CMOS level output * CMOS level Hysteresis input With standby control
R
N-ch
Digital output
Digital input Standby control signal
G
P-ch N-ch
* CMOS level input Without standby control
R
Digital input
H
P-ch N-ch
* CMOS level Hysteresis input Without standby control
R
Digital input
(Continued)
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MB91101/MB91101A
(Continued)
Type I Circuit Remarks * CMOS level output * CMOS level Hysteresis input Without standby control
P-ch N-ch
Digital output
R
Digital output
Digital input
J
P-ch Digital output
* CMOS level output * TTL level input With standby control
R
N-ch
Digital output
Digital input Standby control signal TTL
K
P-ch Digital output
* CMOS level input/output With standby control * Large current drive
R
N-ch
Digital output
Digital input Standby control signal
L
* CMOS level output
P-ch N-ch
Digital output
Digital output
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MB91101/MB91101A
s HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. Take care that the analog power supply (AVCC , AVR) and the analog input do not exceed the digital power supply (VCC) when the analog power supply turned on or off.
2. Treatment of Unused Pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
3. External Reset Input
It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly.
4. Remarks for External Clock Operation
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at "H" output in stop mode). And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.
* Using an external clock
X0 X1 MB91101
Using an external clock (normal) Note: Can not be used stop mode (oscillation stop mode).
X0 Open X1 MB91101
Using an external clock (can be used at 12.5 MHz and less than.) (5 V power supply only)
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MB91101/MB91101A
5. Power Supply Pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND. It is preferred to connect VCC and VSS of MB91101 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 F between VCC and VSS at a position as close as possible to MB91101. MB91101 has an internal regulator. When using with 5 V power supply, supply 5 V to VCC5 pin and make sure to connect about 0.1 F bypass capacitor to VCC3 pin for regulator. And another 3 V power supply is needed for the A/D convertor. When using with 3 V power supply, connect both VCC5 pin and VCC3 pin to the 3 V power supply.
* Connecting to a power supply
[Using with 5 V power supply] 3V 5V 3V VCC5 AVCC AVRH AVSS VSS GND VCC3 VCC5 AVCC About 0.1 F AVRH AVSS GND VSS VCC3 [Using with 3 V power supply]
6. Crystal Oscillator Circuit
Noises around X0 and X1 pins may cause malfunctions of MB91101. In designing the PC board, layout X0, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for stable operation.
7. Turning-on Sequence of A/D Converter Power Supply and Analog Input
Make sure to turn on the digital power supply (VCC) before turning on the A/D converter (AVCC, AVRH) and applying voltage to analog input (AN0 to AN3). Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies may be turned on simultaneously.) Make sure that AVRH never exceeds AVCC when turning on/off power supplies.
8. Treatment of N.C. Pins
Make sure to leave N.C. pins open.
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MB91101/MB91101A
9. Fluctuation of Power Supply Voltage
Warranty range for normal operation against fluctuation of power supply voltage VCC is as given in rating. However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by controlling power supply as a reference of stabilizing, VCC ripple fluctuation (P-P value) at the commercial frequency (50 Hz to 60 Hz) should be less than 10% of the standard VCC value and the transient regulation should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply.
10. Mode Setting Pins (MD0 to MD2)
Connect mode setting pins (MD0 to MD2) directly to VCC or VSS. Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.
11. Internal DC Regulator
Internal DC regulator stops in stop mode. When the regulator stops owing to the increase of inner leakage current (ICCH) in stop mode, malfunction caused by noise or any troubles about power supply in normal operation, the internal 3 V power supply voltage may decrease less than the warranty range for normal operation. So when using the internal regulator and stop mode with 5 V power supply, never fail to support externally so that 3 V power supply voltage might not decrease. However, even in such a case, the internal regulator can be restarted by inputting the reset procedure. (In this case, set the reset to "L" level within the oscillation stabilizing waiting time.) * Using STOP mode with 5 V power supply
5V VCC5 VCC3 VSS 0.1 F approx. 6.8 k
3.6 k
12. Turning on the Power Supply
When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to "H" level.
13. Pin Condition at Turning on the Power Supply
The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation of the internal regulator becomes stable. So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz. Take care that the pin condition may be output condition at initial unstable condition. (With the MB91101A, however, initalization can be achieved in less than about 42 ms after turning on the internal power supply by maintaining the RST pin at "L" level.) 18
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MB91101/MB91101A
14. Source Oscillation Input at Turning on the Power Supply
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting.
15. Hardware Stand-by at Turning on the Power Supply
When turning on the power supply with the HST pin being set to "L" level, the hardware doesn't stand by. However the HST pin becomes available after the reset cancellation, the HST pin must once be back to "H" level.
16. Power on Reset
Make sure to make power on reset at turning on the power supply or returning on the power supply when the power supply voltage is below the warranty range for normal operation.
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MB91101/MB91101A
s BLOCK DIAGRAM
FR CPU
RAM (2 Kbytes)
Bit search module 3 3 3 DMA controller (DMAC) (8 ch.)
D-bus (32 bits)
I-bus (16 bits)
Instruction cache (1 Kbyte)
DREQ0 to DREQ2 DACK0 to DACK2 EOP0 to EOP2
Bus converter (HarvardPrinceton)
Bus converter (32 bits16 bits) 16 25 X0 X1 RST HST Clock control unit (Watchdog timer) 2 Bus controller 6 INT0 to INT3 NMI 4 Interrupt control unit D16 to D31 A00 to A24 RD WR0, WR1 RDY CLK CS0 to CS5 BRQ BGRNT
AN0 to AN3 AVCC AVSS /AVRL AVRH ATG
4 10-bit A/D converter (4 ch.)
C-bus (32 bits)
DRAM controller
Reload timer (3 ch.)
R-bus (16 bits)
RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1
Port 0 to port B Port
Other pins MD0 to MD2, P20 to P27, P60 to P67, P80 to P82, P85, PA1 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7, VCC3, VCC5, VSS
UART (3 ch.) (Baud rate timer)
3 3
SI0 to SI2 SO0 to SO2 SC0 to SC2
PWM timer (4 ch.)
4 4
OCPA0 to OCPA3 TRG0 to TRG3
Note: Pins are display for functions (Actually some pins are multiplexer). When using REALOS, time control should be done by using external interrupt or inner timer. 20
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MB91101/MB91101A
s CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory space. * Memory space
Address 0000 0000H
External ROM/external bus mode I/O area Direct addressing area See "s I/O MAP" I/O area
0000 0400H
0000 0800H Access inhibited 0000 1000H Embedded RAM 0000 1800H
Access inhibited
0001 0000H
External area
FFFF FFFFH
* Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consists of the following areas dependent on accessible data sizes. Byte data access: 000H to 0FFH Half word data access: 000H to 1FFH Word data access: 000H to 3FFH
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MB91101/MB91101A
2. Registers
The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose registers on memory. * Dedicated registers Program counter (PC): Program status (PS): Table base register (TBR): 32-bit length, indicates the location of the instruction to be executed. 32-bit length, register for storing register pointer or condition codes Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) processing. Return pointer (RP): Holds address to resume operation after returning from a subroutine. System stack pointer (SSP): Indicates system stack space. User's stack pointer (USP): Indicates user's stack space. Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division
32 bits PC PS TBR RP SSP USP MDH MDL Program counter Program status Table base register Return pointer System stack pointer User's stack pointer
Initial value XXXX XXXXH
Indeterminate
000F
FC00H Indeterminate
XXXX XXXXH 0000 0000H
XXXX XXXXH XXXX XXXXH XXXX XXXXH
Indeterminate Indeterminate Indeterminate
Multiplication/division result register
* Program status (PS) The PS register is for holding program status and consists of a condition code register (CCR), a system condition code register (SCR) and a interrupt level mask register (ILM).
31 to 21 20 PS --
19
18
17
16 11 to 15 10 -- D1
9 D0
8 T
7 --
6 --
5 S
4 I
3 N
2 Z
1 V
0 C
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
SCR
CCR
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MB91101/MB91101A
* Condition code register (CCR) S-flag: I-flag: N-flag: Z-flag: V-flag: C-flag: Specifies a stack pointer used as R15. Controls user interrupt request enable/disable. Indicates sign bit when division result is assumed to be in the 2's complement format. Indicates whether or not the result of division was "0". Assumes the operand used in calculation in the 2's complement format and indicates whether or not overflow has occurred. Indicates if a carry or borrow from the MSB has occurred.
* System condition code register (SCR) T-flag: Specifies whether or not to enable step trace trap.
* Interrupt level mask register (ILM) ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 0 ILM3 0 ILM2 0 : : 0 1 0 : : 1 1 1 1 1 0 0 ILM1 0 ILM0 0 Interrupt level 0 : : 15 : : 31 Low High-low High
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MB91101/MB91101A
s GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address).
* Register bank structure
32 bits Initial value R0 R1 : : R12 R13 R14 R15 AC (accumulator) FP (frame pointer) SP (stack pointer) XXXX XXXXH : : : : : : : : : : : XXXX XXXXH 0 0 0 0 0 0 0 0H
Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value).
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MB91101/MB91101A
s SETTING MODE
1. Pin
* Mode setting pins and modes Mode setting pins MD2 MD1 MD0 0 0 0 0 1 0 0 1 1 -- 0 1 0 1 -- External vector mode 0 External vector mode 1 -- Internal vector mode -- Mode name Reset vector access area External External -- Internal -- External data bus width 8 bits 16 bits -- (Mode register) -- Bus mode External ROM/external bus mode Inhibited Single-chip mode* Inhibited
* : MB91101 does not support single-chip mode.
2. Registers
* Mode setting registers (MODR) and modes
Address 0000 07FFH M1 M0 * * * * * *
Initial value XXXX XXXXB
Access W
Bus mode setting bit W : Write only X : Indeterminate * : Always write "0" except for M1 and M0.
* Bus mode setting bits and functions M1 0 0 1 1 M0 0 1 0 1 Single-chip mode Internal ROM/external bus mode External ROM/external bus mode -- Inhibited Functions Note
Note: Because of without internal ROM, MB91101 allows "10B" setting value only.
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MB91101/MB91101A
s I/O MAP
Address 0000H 0001H 0002H to 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH to 0011H 0012H 0013H 0014H to 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H SSR0 SIDR0/SODR0 SCR0 SMR0 SSR1 SIDR1/SODR1 SCR1 SMR2 SSR2 SIDR2/SODR2 SCR2 SMR2 Serial status register 0 Serial input register 0/serial output register 0 Serial control register 0 Serial mode register 0 Serial status register 1 Serial input register 1/serial output register 1 Serial control register 1 Serial mode register 1 Serial status register 2 Serial input register 2/serial output register 2 Serial control register 2 Serial mode register 2 PDRE PDRF Port E data register Port F data register (Vacancy) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00001-00B XXXXXXXXB 00000100B 00--0-00B 00001-00B XXXXXXXXB 00000100B 00--0-00B 00001-00B XXXXXXXXB 00000100B 00--0-00B PDR8 Port 8 data register (Vacancy) R/W R/W XXXXXXXXB XXXXXXXXB PDRB PDRA Port B data register Port A data register (Vacancy) R/W - - X - - XXXB PDR6 Port 6 data register (Vacancy) R/W R/W XXXXXXXXB - XXXXXX - B PDR2 Port 2 data register (Vacancy) R/W XXXXXXXXB Register name (abbreviated) Register name (Vacancy) R/W XXXXXXXXB Read/write Initial value
(Continued)
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MB91101/MB91101A
Address 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H 0041H 0042H 0043H 0044H to 0077H
Register name (abbreviated) TMRLR0
Register name 16-bit reload register ch. 0
Read/write W
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMR0
16-bit timer register ch. 0
R
(Vacancy) 16-bit reload timer control status register ch. 0 16-bit reload register ch. 1 ----0000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMCSR0
R/W
TMRLR1
W
TMR1
16-bit timer register ch. 1
R
(Vacancy) 16-bit reload timer control status register ch. 1 A/D converter data register ----0000B 00000000B - - - - - - XXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMCSR1
R/W
ADCR
R
ADCS
A/D converter control status register
R/W
TMRLR2
16-bit reload register ch. 2
W
TMR2
16-bit timer register ch. 2
R
(Vacancy) 16-bit reload timer control status register ch. 2 (Vacancy) ----0000B 00000000B
TMCSR2
R/W
(Continued)
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MB91101/MB91101A
Address 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0080H 0081H 0082H 0083H 0084H to 0093H 0094H 0095H 0096H to 0098H 0099H 009AH to 00D1H 00D2H 00D3H 00D4H to 00DBH 00DCH 00DDH 00DEH 00DFH
Register name (abbreviated) UTIM0/UTIMR0
Register name U-TIMER register ch. 0/reload register ch. 0 (Vacancy)
Read/write R/W
Initial value 00000000B 00000000B
UTIMC0 UTIM1/UTIMR1
U-TIMER control register ch. 0 U-TIMER register ch. 1/reload register ch. 1 (Vacancy)
R/W R/W
0--00001B 00000000B 00000000B
UTIMC1 UTIM2/UTIMR2
U-TIMER control register ch. 1 U-TIMER register ch. 2/reload register ch. 0 (Vacancy)
R/W R/W
0--00001B 00000000B 00000000B
UTIMC2
U-TIMER control register ch. 2 (Vacancy)
R/W
0--00001B
EIRR ENIR
External interrupt cause register Interrupt enable register (Vacancy) External interrupt request level setting register (Vacancy)
R/W R/W
00000000B 00000000B
ELVR
R/W
00000000B
DDRE DDRF
Port E data direction register Port F data direction register (Vacancy)
W W
00000000B 00000000B
GCN1
General control register 1 (Vacancy)
R/W
00110010B 00010000B
GCN2
General control register 2
R/W
00000000B
(Continued)
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MB91101/MB91101A
Address 00E0H 00E1H 00E2H 00E3H 00E4H 00E5H 00E6H 00E7H 00E8H 00E9H 00EAH 00EBH 00ECH 00EDH 00EEH 00EFH 00F0H 00F1H 00F2H 00F3H 00F4H 00F5H 00F6H 00F7H 00F8H 00F9H 00FAH 00FBH 00FCH 00FDH 00FEH 00FFH
Register name (abbreviated) PTMR0
Register name Ch. 0 timer register
Read/write R
Initial value 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000-B 00000000B
PCSR0
Ch. 0 cycle setting register
W
PDUT0 PCNH0 PCNL0 PTMR1
Ch. 0 duty setting register Ch. 0 control status register H Ch. 0 control status register L Ch. 1 timer register
W R/W R/W R
PCSR1
Ch. 1 cycle setting register
W
PDUT1 PCNH1 PCNL1 PTMR2
Ch. 1 duty setting register Ch. 1 control status register H Ch. 1 control status register L Ch. 2 timer register
W R/W R/W R
PCSR2
Ch. 2 cycle setting register
W
PDUT2 PCNH2 PCNL2 PTMR3
Ch. 2 duty setting register Ch. 2 control status register H Ch. 2 control status register L Ch. 3 timer register
W R/W R/W R
PCSR3
Ch. 3 cycle setting register
W
PDUT3 PCNH3 PCNL3
Ch. 3 duty setting register Ch. 3 control status register H Ch. 3 control status register L
W R/W R/W
(Continued)
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MB91101/MB91101A
Address 0100H to 01FFH 0200H 0201H 0202H 0203H 0204H 0205H 0206H 0207H 0208H 0209H 020AH 020BH 020CH to 03E3H 03E4H 03E5H 03E6H 03E7H 03E8H to 03EFH 03F0H 03F1H 03F2H 03F3H 03F4H 03F5H 03F6H 03F7H
Register name (abbreviated)
Register name
Read/write
Initial value
(Vacancy) XXXXXXXXB DPDP DMAC parameter descriptor pointer R/W XXXXXXXXB XXXXXXXXB X0000000B 00000000B DACSR DMAC control status register R/W 00000000B 00000000B 00000000B XXXXXXXXB DATCR DMAC pin control register R/W XXXX 0 0 0 0 B XXXX 0 0 0 0 B XXXX 0 0 0 0 B (Vacancy) --------B ICHCR Instruction cache control register R/W --------B --------B --000000B (Vacancy) XXXXXXXXB BSD0 Bit search module 0-detection data register W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB BSD1 Bit search module 1-detection data register R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
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MB91101/MB91101A
Address 03F8H 03F9H 03FAH 03FBH 03FCH 03FDH 03FEH 03FFH 0400H 0401H 0402H 0403H 0404H 0405H 0406H 0407H 0408H 0409H 040AH 040BH 040CH 040DH 040EH 040FH 0410H 0411H 0412H 0413H 0414H 0415H 0416H
Register name (abbreviated)
Register name
Read/write
Initial value XXXXXXXXB
BSDC
Bit search module transition-detection data register
W
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
BSRR
Bit search module detection result register
R
XXXXXXXXB XXXXXXXXB XXXXXXXXB
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22
Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 Interrupt control register 6 Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Interrupt control register 16 Interrupt control register 17 Interrupt control register 18 Interrupt control register 19 Interrupt control register 20 Interrupt control register 21 Interrupt control register 22
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B
(Continued)
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MB91101/MB91101A
Address 0417H 0418H 0419H 041AH 041BH 041CH 041DH 041EH 041FH 042FH 0430H 0431H 0432H to 047FH 0480H 0481H 0482H 0483H 0484H 0485H 0486H 0487H 0488H 0489H to 0600H 0601H 0602H to 0604H 0605H 0606H 0607H
Register name (abbreviated) ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR47 DICR HRCL
Register name Interrupt control register 23 Interrupt control register 24 Interrupt control register 25 Interrupt control register 26 Interrupt control register 27 Interrupt control register 28 Interrupt control register 29 Interrupt control register 30 Interrupt control register 31 Interrupt control register 47 Delayed interrupt control register Hold request cancel request level setting register (Vacancy)
Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B -------0B ---11111B
RSRR/WTCR STCR PDRR CTBR GCR WPR
Reset cause register/ watchdog peripheral control register Standby control register DMA controller request squelch register Timebase timer clear register Gear control register Watchdog reset occurrence postpone register (Vacancy)
R/W R/W R/W W R/W W
1X X X X - 0 0
B
000111--B ----0000B XXXXXXXX B 110011-1B XXXXXXXXB
PCTR
PLL control register (Vacancy)
R/W
00--0---B
DDR2
Port 2 data direction register (Vacancy)
W
00000000B
DDR6
Port 6 data direction register (Vacancy)
W
00000000B
(Continued)
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MB91101/MB91101A
Address 0608H 0609H 060AH 060BH 060CH 060DH 060EH 060FH 0610H 0611H 0612H 0613H 0614H 0615H 0616H 0617H 0618H 0619H 061AH 061BH 061CH 061DH 061EH 061FH 0620H 0621H 0622H 0623H 0624H 0625H 0626H 0627H
Register name (abbreviated) DDRB DDRA
Register name Port B data direction register Port A data direction register (Vacancy)
Read/write W W
Initial value 00000000B -000000-B
DDR8 ASR1
Port 8 data direction register Area select register 1
W W
--0--000B 00000000B 00000001B 00000000B 00000000B 00000000B 00000010B 00000000B 00000000B 00000000B 00000011B 00000000B 00000000B 00000000B 00000100B 00000000B 00000000B 00000000B 00000101B 00000000B 00000000B ---00111B 0--00000B 00000000B 0--00000B 0--00000B 00000000B - - XXXXXXB 00---000B
AMR1
Area mask register 1
W
ASR2
Area select register 2
W
AMR2
Area mask register 2
W
ASR3
Area select register 3
W
AMR3
Area mask register 3
W
ASR4
Area select register 4
W
AMR4
Area mask register 4
W
ASR5
Area select register 5
W
AMR5 AMD0 AMD1 AMD32 AMD4 AMD5 DSCR RFCR
Area mask register 5 Area mode register 0 Area mode register 1 Area mode register 32 Area mode register 4 Area mode register 5 DRAM signal control register Refresh control register
W R/W R/W R/W R/W R/W W R/W
(Continued)
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MB91101/MB91101A
(Continued)
Address 0628H 0629H 062AH 062BH 062CH 062DH 062EH 062FH 0630H to 07FDH 07FEH 07FFH LER MODR Little endian register Mode register EPCR1 DMCR4 Register name (abbreviated) EPCR0 Register name External pin control register 0 (Vacancy) External pin control register 1 DRAM control register 4 W R/W 11111111B 00000000B 0000000-B 00000000B 0000000-B Read/write W Initial value ----1100B -1111111B
DMCR5
DRAM control register 5
R/W
(Vacancy) W W -----000B XXXXXXXXB
Note: Do not use (vacancy).
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MB91101/MB91101A
s INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes Reset Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Exception for undefined instruction NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 UART0 receive complete UART1 receive complete UART2 receive complete UART0 transmit complete UART1 transmit complete UART2 transmit complete DMAC0 (complete, error) DMAC1 (complete, error) DMAC2 (complete, error) DMAC3 (complete, error) DMAC4 (complete, error) DMAC5 (complete, error) Interrupt number Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Interrupt level Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H
(Continued)
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MB91101/MB91101A
Interrupt causes DMAC6 (complete, error) DMAC7 (complete, error) A/D converter (successive approximation conversion type) 16-bit reload timer 0 16-bit reload timer 1 16-bit reload timer 2 PWM 0 PWM 1 PWM 2 PWM 3 U-TIMER 0 U-TIMER 1 U-TIMER 2 Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Delayed interrupt cause bit
Interrupt number Decimal 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Hexadecimal 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Interrupt level Register ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 Offset 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H
TBR default address 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H
(Continued)
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MB91101/MB91101A
(Continued)
Interrupt causes Reserved for system (used in REALOS*) Reserved for system (used in REALOS*) Used in INT instructions Interrupt number Decimal 64 65 66 to 255 Hexadecimal 40 41 42 to FF Interrupt level Register -- -- -- Offset 2FCH 2F8H 2F4H to 000H TBR default address 000FFEFCH 000FFEF8H 000FFEF4H to 000FFC00H
* : When using in REALOS/FR, interrupt 0x40, 0x41 for system code.
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MB91101/MB91101A
s PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register (DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit "0" specifies input and "1" specifies output. * For input (DDR = "0") setting; PDR reading operation: reads level of corresponding external pin. PDR writing operation: writes set value to PDR. * For output (DDR = "1") setting; PDR reading operation: reads PDR value. PDR writing operation: outputs PDR value to corresponding external pin. * Block diagram
Resource input
0
1 PDR read Data bus 0 PDR (Port data register) Resource output 1 Pin
Resource output enable DDR (Data direction register)
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MB91101/MB91101A
* Port data register
Address 000001H 000005H 00000BH 000009H 000008H 000012H 000013H
bit 7 PDR2 PDR6 PDR8 PDRA PDRB PDRE PDRF
bit 0
Initial value XXXXXXXX XXXXXXXX - - X - - XXX - XXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
B
B
B
B
B
B
( ) : Access R/W : Readable and writable X : Indeterminate
* Data direction register
Address 000601H 000605H 00060BH 000609H 000608H 0000D2H 0000D3H
bit 7 DDR2 DDR6 DDR8 DDRA DDRB DDRE DDRF
bit 0
Initial value 00000000 00000000 - - 0 - - 000 - 000000 00000000 00000000 00000000
B
(W) (W) (W) (W) (W) (W) (W)
B
B
B
B
B
B
( ) : Access W : Write only - : Unused
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MB91101/MB91101A
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. * * * * * * * 8 channels Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer Transfer all through the area Max. 65536 of transfer cycles Interrupt function right after the transfer Selectable for address transfer increase/decrease by the software External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each
* Block diagram
DREQ0 to DREQ2
3
Edge/level detection circuit
3
3 3 Sequencer 8
DACK0 to DACK2 EOP0 to EOP2 Interrupt request
5 Inner resource Transfer request
Data buffer
Switcher
DPDP
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
40
Data bus
DACSR
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MB91101/MB91101A
* Registers (DMAC internal registers)
Address 00000200H 00000201H 00000202H 00000203H 00000204H 00000205H 00000206H 00000207H 00000208H 00000209H 0000020AH 0000020BH bit 31 bit 16 DPDP bit 0
Initial value XXXXXXXX XXXXXXXX XXXXXXXX X0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B B B B B B B B B B B B
(R/W)
DACSR
(R/W)
DATCR
XXXXXXXX XXXX0 0 0 0 XXXX0 0 0 0 XXXX0 0 0 0
(R/W)
( ) : Access R/W : Readable and writable X : Indeterminate
* Registers (DMA descriptor)
Address DPDP + 0H
bit 31
bit 0 DMA ch.0 Descriptor
DPDP + 0CH
DMA ch.1 Descriptor
DPDP + 54H
DMA ch.7 Descriptor
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MB91101/MB91101A
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication, and it has the following features. The MB91101 consists of 3 channels of UART. * * * * * * * * Full double double buffer Both a synchronous (start-stop system) communication and CLK synchronous communication are available. Supporting multi-processor mode Perfect programmable baud rate Any baud rate can be set by internal timer (refer to section "4. U-TIMER"). Any baud rate can be set by external clock. Error checking function (parity, framing and overrun) Transfer signal: NRZ code Enable DMA transfer/start by interrupt.
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MB91101/MB91101A
* Block diagram
Control signals Receive interrupt (to CPU) SC (clock) Transmit clock From U-TIMER Clock select circuit Receive clock Transmit interrupt (to CPU)
From external clock SC Receive control circuit Transmit control circuit
SI (receive data)
Start bit detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SO (transmit data)
Receive status judge circuit
Receive shifter
Transmit shifter
Receive error generate signal for DMA (to DMAC)
Receive complete SIDR
Transmit start SODR
R-bus
MD1 MD0 SMR register CS0 SCKE SOE SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
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MB91101/MB91101A
* Register configuration
Address 0000001EH 00000022H 00000026H 0000001FH 00000023H 00000027H 0000001CH 00000020H 00000024H 0000001DH 00000021H 00000002H
bit 15 SCR0 SCR1 SCR2
bit 8
bit 0
Initial value 00000100 00000100 00000100
B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
B
B
SMR0 SMR1 SMR2 SSR0 SSR1 SSR2 SIDR0/SODR0 SIDR1/SIDR1 SIDR2/SIDR2
00 - - 0 - 00 00 - - 0 - 00 00 - - 0 - 00 00001 - 00 00001 - 00 00001 - 00 XXXXXXXX XXXXXXXX XXXXXXXX
B
B
B
B
B
B
B
B
B
() R/W - X
: : : :
Access Readable and writable Unused Indeterminate
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MB91101/MB91101A
4. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91101 has 3 channel U-TIMER embedded on the chip. An interval of up to 216 x can be counted. * Block diagram
bit 15
bit 0
UTIMR (reload register)
Load bit 15 bit 0
UTIM ( U-TIMER register) Underflow (Peripheral clock) Clock Control
f.f.
To UART
* Register configuration
Address 00000078H 00000079H 0000007CH 0000007DH 00000080H 00000081H 0000007BH 0000007FH 00000083H
bit 15 UTIM0/UTIMR0 UTIM1/UTIMR1 UTIM2/UTIMR2 UTIMC0 UTIMC1 UTIMC2
bit 0
Initial value 00000000 00000000 00000000 00000000 00000000 00000000 0 - - 00001 0 - - 00001 0 - - 00001
B B B B B B B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
B
B
( ) : Access R/W : Readable and writable - : Unused
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MB91101/MB91101A
5. PWM Timer
The PWM timer can output high accurate PWM waves efficiently. MB91101 has inner 4-channel PWM timers, and has the following features. * Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16bit compare resister with a buffer for duty setting, and a pin controller. * The count clock of a 16-bit down counter can be selected from the following four inner clocks. Inner clock , /4, /16, /64 * The counter value can be initialized "FFFFH" by the resetting or the counter borrow. * PWM output (each channel) * Resister description * Block diagram (general construction)
16-bit reload timer ch.0
TRG input PWM timer ch.0
PWM0
16-bit reload timer ch.1
General control register 1 (cause selection) 4
TRG input PWM timer ch.1
PWM1
General control register 2
TRG input PWM timer ch.2
PWM2
4 External TRG0 to TRG3
TRG input PWM timer ch.3
PWM3
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MB91101/MB91101A
* Block diagram (for one channel)
PCSR
PDUT
Prescaler 1/1 1/4 1 / 16 1 / 64
ck 16-bit down counter Start
cmp Load
Borrow
PPG mask S Peripheral clock Q
PWM output
R
Reverse bit Interrupt selection Enable TRG input Edge detect Soft trigger
IRQ
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MB91101/MB91101A
* Register configuration
Address bit 15 000000DCH 000000DDH 000000DFH 000000E0H 000000E1H 000000E2H 000000E3H 000000E4H 000000E5H 000000E6H 000000E7H 000000E8H 000000E9H 000000EAH 000000EBH 000000ECH 000000EDH 000000EEH 000000EFH 000000F0H 000000F1H 000000F2H 000000F3H 000000F4H 000000F5H 000000F6H 000000F7H 000000F8H 000000F9H 000000FAH 000000FBH 000000FCH 000000FDH 000000FEH 000000FFH PCNH3 PCNL3 PTMR3 PCSR3 PDUT3 PCNH2 PCNL2 PTMR2 PCSR2 PDUT2 PCNH1 PCNL1 PTMR1 PCSR1 PDUT1 PCNH0 PCNL0 PTMR0 PCSR0 PDUT0 bit 8 GCN1 GCN2 bit 0
Initial value 00110010 00010000 00000000 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000 00000000 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000 00000000 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000 00000000 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000 00000000
B B B B B B B B B B
(R/W) (R/W) (R) (W) (W) (R/W) (R/W) (R) (W) (W) (R/W) (R/W) (R) (W) (W) (R/W) (R/W) (R) (W) (W) (R/W) (R/W)
B B B B B B B B
B B B B B B B B
B B B B B B B B
B
() R/W R W - X
: : : : : :
Access Readable and writable Read only Write only Unused Indeterminate
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MB91101/MB91101A
6. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). The DMA transfer can be started by the interruption. The MB91101 consists of 3 channels of the 16-bit reload timer. * Block diagram
16 16-bit reload register 8 Reload RELD 16 16-bit down counter UF OUTE OUTL 2 GATE R-bus CSL1 Clock selector CSL0 2 Retrigger IN CTL. EXCK --- 21 2 3 2 5 Internal clock MOD0 3 3 Prescaler clear MOD2 MOD1 PWM (ch.0, ch.1) A/D (ch.2) TRG CNTE OUT CTL. 2 INTE UF IRQ
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MB91101/MB91101A
* Register configuration
Address 0000002EH 0000002FH 00000036H 00000037H 00000042H 00000043H 0000002AH 0000002BH 00000032H 00000033H 0000003EH 0000003FH 00000028H 00000029H 00000030H 00000031H 0000003CH 0000003DH
bit 15 TMCSR0 TMCSR1 TMCSR2 TMR0 TMR1 TMR2 TMRLR0 TMRLR1 TMRLR2
bit 0
Initial value - - - - 0000 00000000 - - - - 0000 00000000 - - - - 0000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
B B B B B B B B B B B B B B B B B B
(R/W) (R/W) (R/W) (R) (R) (R) (W) (W) (W)
() R/W R W - X
: : : : : :
Access Readable and writable Read only Write only Unused Indeterminate
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MB91101/MB91101A
7. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. * Block diagram
Input latch
Address decoder
Detection mode
D-bus
Single-detection data recovery
Bit search circuit
Search result
* Register configuration
Address 000003F0H 000003F1H 000003F2H 000003F3H 000003F4H 000003F5H 000003F6H 000003F7H 000003F8H 000003F9H 000003FAH 000003FBH 000003FCH 000003FEH 000003FDH 000003FFH () R/W R W X : : : : : Access Readable and writable Read only Write only Indeterminate Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
bit 31
bit 16
bit 0
BSD0
(W)
BSD1
(W)
BSDC
(W)
BSRR
(W)
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MB91101/MB91101A
8. 10-bit A/D Converter (Successive Approximation Conversion Type)
The A/D converter is the module which converts an analog input voltage to a digital value, and it has following features. * * * * Minimum converting time: 5.6 s/ch. (system clock: 25 MHz) Inner sample and hold circuit Resolution: 10 bits Analog input can be selected from 4 channels by program. Single convert mode: 1 channel is selected and converted. Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable. Continuous convert mode: Converting the specified channel repeatedly. Stop convert mode: After converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. * DMA transfer operation is available by interruption. * Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer (rising edge).
* Block diagram
AVCC AVR AVSS
Internal voltage generator MPX
AN0 AN1 AN2 AN3 R-bus Decoder Data register (ADCR) A/D control register (ADCS) Trigger start ATG TIM0 (internal connection) (16-bit reload timer ch.2) (Peripheral clock) Timer start Operating clock Prescaler Sample & hold circuit Input circuit Successive approximation register
Comparator
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MB91101/MB91101A
* Register configuration
Address 0000003AH 0000003BH 00000038H 00000039H () R/W R - X : : : : :
bit 15 ADCS ADCR
bit 0
Initial value 00000000 00000000 - - - - - - XX XXXXXXXX
B B B B
(R/W) (R)
Access Readable and writable Read only Unused Indeterminate
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MB91101/MB91101A
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts. * Block diagram
INT0*2
IM
OR NMI NMI processing 4 Level judgment RI00 * * * RI47 (DLYIRQ) DLYI*1 * * * ICR00
Priority judgment 5 5 LEVEL4 to LEVEL0*4
6 * * ICR47 Vector judgment
Level vector generation
HLDREQ cancel request
HLDCAN*3
6
VCT5 to VCT0*5
R-bus
*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section "11. Delayed Interrupt Module" for detail). *2: INT0 is a wake-up signal to clock control block in the sleep or stop status. *3: HLDCAN is a bus release request signal for bus masters other than CPU. *4: LEVEL5 to LEVEL0 are interrupt level outputs. *5: VCT5 to VCT0 are interrupt vector outputs.
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MB91101/MB91101A
* Register configuration
Address 00000400H 00000401H 00000402H 00000403H 00000404H 00000405H 00000406H 00000407H 00000408H 00000409H 0000040AH 0000040BH 0000040CH 0000040DH 0000040EH 0000040FH 00000410H
bit 7 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16
bit 0
Initial value - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W)
Address 00000411H 00000412H 00000413H 00000414H 00000415H 00000416H 00000417H 00000418H 00000419H 0000041AH 0000041BH 0000041CH 0000041DH 0000041EH 0000041FH 0000042FH 00000431H 00000430H
bit 7 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR47 HRCL DICR
bit 0
Initial value - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - - - - - 0 B (R/W)
( ) : Access R/W : Redable and writable - : Unused
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MB91101/MB91101A
10. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to INT3 pins. Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI pin). * Block diagram
8 Interrupt enable register 9 Gate R-bus 8 Interrupt cause register 8 Request level setting register Cause F/F Edge detection circuit 5
Interrupt request
INT0 to INT3 NMI
* Register configuration
Address 00000095H 00000094H 00000099H
bit 15
bit 8 ENIR EIRR ELVR
bit 0
Initial value 00000000 B 00000000 B 00000000 B (R/W) (R/W) (R/W)
( ) : Access R/W : Redable and writable
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MB91101/MB91101A
11. Delayed Interrupt Module
Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed interrupt module, an interrupt request to CPU can be generated/cancelled by the software. Refer to the section "9. Interrupt Controller" for delayed interrupt module block diagram. * Register configuration
Address 00000430H
bit 7 DICR
bit 0
Initial value -------0
B
(R/W)
( ) : Access R/W : Redable and writable - : Unused
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MB91101/MB91101A
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions. * * * * * * CPU clock generation (including gear function) Peripheral clock generation (including gear function) Reset generation and cause hold Standby function (including hardware standby) DMA request prohibit PLL (multiplier circuit) embedded
* Block diagram
[Gear control block] Gear control register (GCR) CPU gear R-bus PCTR register PLL 1/2 Peripheral gear CPU clock Internal bus clock External bus clock Peripheral DMA clock Internal peripheral clock Selection circuit
X0 X1
Oscillator circuit
Internal clock generation circuit
Internal interrupt request Internal reset
[Stop/sleep control block]
Standby control register (STCR) STOP state CPU hold enable HST pin Status transition control circuit Reset generation F/F [DMA prohibit circuit] DMA request DMA request prohibit register (PDRR) [Reset cause circuit] Power on sel SLEEP state CPU hold request Internal reset
RST pin
Reset cause register (RSRR) [Watchdog control block] Watchdog reset generation postpone register (WPR) Watchdog reset postpone register Timebase timer clear register (CTBR) Timebase timer Count clock
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MB91101/MB91101A
* Register configuration
Address 00000480H 00000481H 00000482H 00000483H 00000484H 00000485H 00000488H () R/W W - X : : : : :
bit 15 RSRR/WTCR
bit 8
bit 0
Initial value 1XXXX - 0 0
B
(R/W) (R/W) (R/W) (W) (R/W) (W) (R/W)
STCR PDRR CTBR GCR WPR PCTR
000111 - - - - - 0000 XXXXXXXX 110011 - 1 XXXXXXXX 00 - - 0 - - -
B
B
B
B
B
B
Access Redable and writable Write only Unused Indeterminate
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MB91101/MB91101A
13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the external I/O, and has the following features. * 25-bit (32 Mbytes) address output * 6 independent banks owing to the chip select function. Can be set to anywhere on the logical address space for minimum unit 64 Kbytes. Total 32 Mbytes x 6 area setting is available by the address pin and the chip select pin. * 8/16-bit bus width setting are available for every chip select area. * Programmable automatic memory wait (max. for 7 cycles) can be inserted. * DRAM interface support Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F) Single CAS DRAM Hyper DRAM 2 banks independent control (RAS, CAS, etc. control signals) DRAM select is available from 2CAS/1WE and 1CAS/2WE. Hi-speed page mode supported CBR/self refresh supported Programmable wave form * Unused address/data pin can be used for I/O port. * Little endian mode supported * Clock doubler: Internal bus 50 MHz, external bus 25 MHz
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MB91101/MB91101A
* Block diagram
Address bus 32
Data bus 32
A-OUT External data bus Write buffer Switch MUX
Read buffer
Switch
DATA BLOCK ADDRESS BLOCK External address bus
+1 or +2 Inpage Address buffer Shifter 6 Comparator
ASR AMR
CS0 to CS5
DRAM control DMCR Underflow Refresh counter To TBT
8
RAS0, RAS1 CS0L, CS1L CS0H, CS1H DW0, DW1
3 External pin control block All blocks control 4 Registers and control
RD WR0, WR1 BRQ BGRNT CLK RDY
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MB91101/MB91101A
* Register configuration
Address bit 31 0000060CH 0000060DH 0000060EH 0000060FH 00000610H 00000611H 00000612H 00000613H 00000614H 00000615H 00000616H 00000617H 00000618H 00000619H 0000061AH 0000061BH 0000061CH 0000061DH 0000061EH 0000061FH 00000620H 00000621H 00000622H 00000623H 00000624H 00000625H 00000626H 00000627H 00000628H 00000629H 0000062BH 0000062CH 0000062DH 0000062EH 0000062FH 000007FEH 000007FFH LER MODR DMCR4 DMCR5 EPCR0 EPCR1 AMD5 DSCR RFCR AMD0 AMD1 AMD32 AMD4 ASR5 AMR5 ASR4 AMR4 ASR3 AMR3 ASR2 AMR2 ASR1 AMR1 bit 16 bit 0
Initial value 00000000 00000001 00000000 00000000 00000000 00000010 00000000 00000000 00000000 00000011 00000000 00000000 00000000 00000100 00000000 00000000 00000000 00000101 00000000 00000000 - - - 00111 0 - - 00000 00000000 0 - - 00000 0 - - 00000 00000000 - - XXXXXX 00 - - - 000 - - - - 1100 - 1111111 11111111 00000000 0000000 00000000 0000000 - - - - - 000 XXXXXXXX
B B B B B B B B B B B B B B B B B B B B
(W) (W) (W) (W) (W) (W) (W) (W) (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (W) (W) (R/W) (R/W) (W) (W)
B
B
B
B
B
B
B B B B
B
B B B B B
B
() R/W W - X
: : : : :
Access Redable and writable Write only Unused Indeterminate
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MB91101/MB91101A
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter At 5 V power supply Power supply voltage At 3 V power supply Analog supply voltage Analog reference voltage Analog pin input voltage Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current "H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature *1: *2: *3: *4: *5: Symbol VCC5 VCC3 VCC5 VCC3 AVCC AVRH VIA VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Value Min. VSS - 0.3 -- VCC3 - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- 0 -55 Max. VSS + 6.5 -- VSS + 6.5 VSS + 3.6 VSS + 3.6 VSS + 3.6 AVCC + 0.3 VCC5 + 0.3 VCC5 + 0.3 10 4 100 50 -10 -4 -50 -20 500 +70 +150 Unit V V V V V V V V V mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *3 *4 *1 *1 *2 *2 Remarks
VCC5 must not be less than VSS - 0.3 V. Make sure that the voltage does not exceed VCC5 + 0.3 V, such as when turning on the device. Maximum output current is a peak current value measured at a corresponding pin. Average output current is an average current for a 100 ms period at a corresponding pin. Average total output current is an average current for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended Operating Conditions
(1) At 5 V operation (4.5 V to 5.5 V) (VSS = AVSS = 0.0 V) Parameter Symbol VCC5 Power supply voltage VCC5 VCC3 Analog supply voltage Analog reference voltage Operating temperature Smoothing capacitor AVCC AVRH TA CS Value Min. 4.5 *1 -- VSS + 2.7 VSS - 0.3 0 0.1 Max. 5.5 *1 -- VCC + 3.6 AVCC +70 1.0 Unit V V V V V C F VCC3 pin *2 Remarks Normal operation Retaining the RAM state in stop mode *2
*1: At VCC5, the RAM state holding is not warranted in stop mode. *2: VCC3 is used for the bypass capacitor pin. *3: Use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic capacitor. And select the larger capacity smoothing condenser to connect to the power supply (VCC5) than CS. (2) At 3 V operation (2.7 V to 3.6 V) (VSS = AVSS = 0.0 V) Parameter Symbol VCC5 Power supply voltage VCC5 VCC3 Analog power supply voltage Analog reference voltage Operating temperature AVCC AVRH TA Value Min. 2.7 2.7 2.7 VSS + 2.7 AVSS 0 Max. 3.6 3.6 3.6 VCC + 3.6 AVCC +70 Unit V V V V V C Remarks Normal operation Retaining the RAM state in stop mode *
* : Connect to VCC5 for the power supply pin. * Connecting to a power supply
Using with 5 V power supply 3V 5V 3V VCC5 AVCC AVRH AVSS VSS GND VCC3 VCC5 AVCC About 0.1 F AVRH AVSS GND VSS VCC3 Using with 3 V power supply
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MB91101/MB91101A
VCC (V) Power supply at 5 V
Normal operation warranty range (TA = 0C to +70C) Net masked area are fCPP.
5.5 Supply voltage 4.5 3.6 3.3 3.0 2.7
Power supply at 3 V
3.0 V 0.3 V
3.3 V 0.3 V fCP/fCPP (MHz)
0
0.625 fCP/fCPP (MHz)
25 Internal clock
40
50
Max. internal clock frequency setting
fCP
50 CPU 40 PLL system (4 multiplication)
fCPP
25 20 12.5 5 0 0
Peripheral Divide-by-2 system
10 12.5
25 External clock Self-oscillation
50
fC (MHz)
Source oscillating input clock
Notes: * When using PLL, the external clock must be used between 10.0 MHz to 12.5 MHz. * PLL oscillation stabilizing period > 100 s * The setting of internal clock must be within above ranges.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
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MB91101/MB91101A
3. DC Characteristics
(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name Input pin except for hysteresis input HST, NMI, RST, PA1 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7 Input other than following symbols HST, NMI, RST, PA1 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7 D16 to D31, A00 to A24, P6 to PF D16 to D31, A00 to A24, P6 to PF D00 to D31, A00 to A23, P8 to PF RST VCC VCC VCC Except for VCC5, VCC3, AVCC, AVSS, VSS Condition Value Min.
0.65 x VCC3
Typ. --
Max.
VCC5 + 0.3
Unit
Remarks
VIH "H" level input voltage VIHS
--
V
*
--
0.8 x VCC3
--
VCC5 + 0.3
V
Hysteresis input *
VIL "L" level input voltage VILS
--
VSS - 0.3
--
0.25 x VCC3
V
*
--
VSS - 0.3
--
0.2 x VCC3
V
Hysteresis input *
"H" level output VOH voltage "L" level output voltage VOL
VCC5 = 4.5 V IOH = -4.0 mA VCC5 = 4.5 V IOL = 4.0 mA VCC5 = 5.5 V 0.45 V < VI < VCC VCC5 = 5.5 V VI = 0.45 V FC = 12.5 MHz VCC5 = 5.5 V FC = 12.5 MHz VCC5 = 5.5 V TA = +25C VCC5 = 5.5 V --
VCC - 0.5
--
--
V
--
--
0.4
V
Input leakage current ILI (Hi-Z output leakage current) Pull-up resistance RPULL ICC Power supply current ICCS ICCH Input capacitance CIN
-5
--
+5
A
25 -- -- -- --
50 75 40 10 10
100 100 60 100 --
k
(4 multiplication)
mA Operation at 50 MHz mA Sleep mode A Stop mode pF
* : VCC3 = 3.3 0.2 V (internal regulator output voltage) when using 5 V power supply, VCC3 = power supply voltage when using 3 V power supply (internal regulator unused)
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MB91101/MB91101A
4. AC Characteristics
Measurement Conditions * VCC = 5.0 V 10% Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Symbol VIH VIL VOH VOL Value Min. -- -- -- -- Typ. 2.4 0.8 2.4 0.8 Max. -- -- -- -- Unit V V V V Remarks
VCC
Input VIH VIL
Output VOH VOL
0.0 V
* VCC = 2.7 V to 3.6 V Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Symbol VIH VIL VOH VOL Value Min. -- -- -- -- Typ. 1/2 x VCC 1/2 x VCC 1/2 x VCC 1/2 x VCC Max. -- -- -- -- Unit V V V V Remarks
VCC
Input VIH VIL
Output VOH VOL
0.0 V
* Load conditions
Output pin C = 50 pF
(VCC = 5.0V 10%)
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MB91101/MB91101A
* Load capacitance - Delay characteristics (Output delay with reference to the internal)
(ns) 35 5 V Fall 30 3 V Rise 25 20 15 10 5 0 0 20 40 50 60 80 100 120 C (pF) 5 V Rise
3 V Fall
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MB91101/MB91101A
(1) Clock Timing Rating (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol fC Clock frequency fC fC Clock cycle time Frequency shift ratio (when locked) tC tC f PWH, PWL PWH, PWL Input clock rising/falling time Internal operating clock frequency tCR, tCF fCP fCPB fCPP tCP Internal operating clock cycle time tCPB tCPP Pin name X0, X1 X0, X1 X0, X1 X0, X1 X0, X1 -- Condition When using PLL Self-oscillation (divide-by-2 input) External clock (divide-by-2 input) When using PLL -- When using PLL Value Min. 10 10 10 80 40 -- Max. 12.5 25 25 100 100 5 Unit MHz MHz MHz ns ns % *1 Input to X0 only, when using 5 V power supply Input to X0, X1 (tCR + tCF) Remarks
X0, X1 -- X0, X1 X0, X1 -- -- -- -- -- -- CPU system Bus system Peripheral system CPU system Bus system Peripheral system
25
--
ns
Input clock pulse width
10 -- 0.625*2 0.625* 20 40*3 40
2
-- 8 50 25* 25 1600*2 1600*2 1600*2
3
ns ns MHz MHz MHz ns ns ns
0.625*2
*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system.
+ +
f
=
|| x 100 (%) f0
Center frequency f 0 - -
*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and a 1/8 gear. *3: Values when using the doubler and CPU operation at 50 MHz.
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MB91101/MB91101A
* Clock timing rating measurement conditions
tC 0.8 VCC 0.2 VCC PWH tCF PWL tCR
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MB91101/MB91101A
(2) Clock Output Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name tCYC Cycle time CLK CLK CLK CLK tCYC tCHCL tCLCH CLK CLK CLK CLK Condition -- Using the doubler -- Value Min. tCP tCPB Max. -- -- Unit ns ns ns ns *2 *3 Remarks *1
1/2 x tCYC - 10 1/2 x tCYC + 10 1/2 x tCYC - 10 1/2 x tCYC + 10
, tCP tCPB (internal operating clock cycle time): Refer to "(1) Clock Timing Rating." *1: tCYC is a frequency for 1 clock cycle including a gear cycle. Use the doubler when CPU frequency is above 25 MHz. *2: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively. Min. : (1 - n/2) x tCYC - 10 Max. : (1 - n/2) x tCYC + 10 Select a gear cycle of x 1 when using the doubler. *3: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8, respectively. Min. : n/2 x tCYC - 10 Max. : n/2 x tCYC + 10 Select a gear cycle of x 1 when using the doubler.
tCYC tCHCL CLK VOH VOL tCLCH VOH
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MB91101/MB91101A
The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows: However, in this chart source oscillation input means X0 input clock.
Source oscillation input (when using the doublure) (1) PLL system (CHC bit of GCR set to "0") (a) Gear x 1 CLK pin CCK1/0: "00" tCYC
Source oscillation input (2) 2 dividing system (CHC bit of GCR set to "1") (a) Gear x 1 CLK pin CCK1/0: "00" (b) Gear x 1/2 CLK pin CCK1/0: "01" (c) Gear x 1/4 CLK pin CCK1/0: "10" (d) Gear x 1/8 CLK pin CCK1/0: "11" tCYC
tCYC
tCYC
tCYC
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MB91101/MB91101A
* Ceramic oscillator applications
Recommended circuit (2 contacts) Recommended circuit (3 contacts)
X0 *
X1
X0 *
X1
C1
C2
C1
C2
C1, C2 internally connected.
* : Murata Mfg. Co., Ltd.
* Discreet type Oscillation frequency [MHz] CSA 5.00 to 6.30 CST CSA CST CSA 6.31 to 10.0 CST CSA CST CSA 10.1 to 13.0 CST CSA CST 13.01 to 15.00 CSA CST Model MG MGW MG093 MGW093 MTZ MTW MTZ093 MTW093 MTZ MTW MTZ093 MTW093 MXZ040 MXW0C3 Load capacitance C1 = C2 [pF] 30 (30) 30 (30) 30 (30) 30 (30) 30 (30) 30 (30) 15 (15) Power supply voltage VCC5 [V] 2.9 to 5.5
2.7 to 5.5
2.9 to 5.5
2.7 to 5.5
3.0 to 5.5
2.9 to 5.5
3.2 to 5.5
( ): C1 and C2 internally connected 3 contacts type.
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MB91101/MB91101A
(3) Reset/Hardware Standby Input Ratings (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Reset input time Hardware standby input time Symbol Pin name Condition tRSTL tHSTL RST HST -- Value Min. tCP x 5 tCP x 5 Max. -- -- Unit ns ns Remarks
tCP (internal operating clock cycle time): Refer to "(1) Clock Timing Rating."
tRSTL, tHSTL
RST HST
0.2 VCC 0.2 VCC
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MB91101/MB91101A
(4) Power on Supply Specifications (Power-on Reset) (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name tR Power supply rising time tR tR tR Power supply shut off time Oscillation stabilizing time tOFF tOSC VCC VCC VCC VCC VCC -- -- Condition VCC = 5.0 V VCC = 3.0/ 3.3 V Value Min. 50 -- 50 -- 1 2 x tC x 221 + 100 s Max. -- 30 -- 18 -- -- Unit s ms s ms ms ns * * * * Repeated operations Remarks
tC (clock cycle time): Refer to "(1) Clock Timing Rating." * : VCC < 0.2 V before the power supply rising
tR
VCC
0.9 x VCC 0.2 V tOFF
Note: Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage.
VCC
A voltage rising rate of 50 mV/ms or less is recommended.
VSS
42 ms approx. 336 ms approx. (@12.5 MHz)
VCC
Regulator Stabilizing time *
(Oscillation stabilizing time) tOSC
RST
tRSTL + (tC x 219) tRSTL: Reset input time *: Reset can't be done during regulator stabilizing time.
Note: Set RST pin to "L" level when turning on the device, at least the described above duration after the supply voltage reaches Vcc is necessary before turning the RST to "H" level.
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MB91101/MB91101A
(5) Normal Bus Access Read/write Operation (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol tCHCSL CS0 to CS5 delay time tCHCSH Address delay time Data delay time RD delay time tCHAV tCHDV tCLRL tCLRH tCLWL WR0, WR1 delay time tCLWH Valid address valid data input time tAVDV Pin name CLK, CS0 to CS5 CLK, CS0 to CS5 CLK, A24 to A00 CLK, D31 to D16 CLK, RD CLK, RD CLK, WR0, WR1 CLK, WR0, WR1 A24 to A00, D31 to D16 RD, D31 to D16 RD, D31 to D16 RD, D31 to D16 -- Condition Value Min. -- -- -- -- -- -- -- -- -- -- 10 0 Max. 15 15 15 15 6 6 6 6 3/2 x tCYC - 25 tCYC - 10 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1 Remarks
RD valid data input time tRLDV Data set up RD time RD data hold time tDSRH tRHDX
tCYC (a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing." *1: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC x extended cycle number for delay) to this rating. *2: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (2 - n/2) x tCYC - 25
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MB91101/MB91101A
BA1 tCYC
BA2
CLK
VOH
VOL
VOH
VOL
VOH
tCHCSL
tCHCSH VOH
CS0 to CS5
VOL
tCHAV
A24 to A00
VOH VOL
VOH VOL
tCLRL
tCLRH VOH
RD
VOL tRLDV
tRHDX tAVDV
D31 to D16
VIH VIL
Read
VIH VIL tDSRH
tCLWL
WR0, WR1
VOL
VOH tCLWH
tCHDV
D31 to D16
VOH VOL
Write
VOH VOL
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MB91101/MB91101A
(6) Ready Input Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name RDY, CLK RDY, CLK Condition -- Value Min. 15 0 Max. -- -- Unit ns ns Remarks
RDY set up time CLK tRDYS CLK RDY hold time tRDYH
tCYC
CLK
VOH
VOL tRDYS
VOH tRDYH
VOL tRDYS tRDYH
RDY When wait(s) is inserted.
VIL
VIH
VIL
VIH
RDY When no wait is inserted.
VIH
VIL
VIH
VIL
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MB91101/MB91101A
(7) Hold Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name Condition tCHBGL BGRNT delay time tCHBGH Pin floating BGRNT time BGRNT pin valid time tXHAL tHAHV CLK, BGRNT CLK, BGRNT BGRNT BGRNT -- Value Min. -- -- tCYC - 10 tCYC - 10 Max. 6 6 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks
tCYC (a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing." Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC
CLK
VOH
VOH
VOH
VOH
BRQ
tCHBGL VOH
tCHBGH
BGRNT
tXHAL
VOL
tHAHV VOH VOL
Each pin
VOH VOL
High impedance
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MB91101/MB91101A
(8) Normal DRAM Mode Read/Write Cycle (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time Output data delay time RAS valid data input time CAS valid data input time CAS data hold time Symbol tCLRAH tCHRAL tCLCASL tCLCASH tCHRAV tCHCAV tCHDWL tCHDWH tCHDV1 tRLDV tCLDV tCADH Pin name CLK, RAS CLK, RAS CLK, CAS CLK, CAS CLK, A24 to A00 CLK, A24 to A00 CLK, DW CLK, DW CLK, D31 to D16 RAS, D31 to D16 CAS, D31 to D16 CAS, D31 to D16 -- Condition Value Min. -- -- -- -- -- -- -- -- -- -- -- 0 Max. 6 6 6 6 15 15 15 15 15 5/2 x tCYC - 16 tCYC - 17 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1 Remarks
tCYC (a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing." CAS: CS0L to CS1H pins are for CAS signal outputs. DW: DW0, DW1 and CS0H to CS1H are used for WE outputs. *1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating. *2: Rating at a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively. Equation: (3 - n/2) x tCYC - 16
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MB91101/MB91101A
Q1 tCYC
Q2
Q3
Q4
Q5
CLK
VOH
VOL
VOH
VOH
VOH
VOL
VOL
VOH
RAS
tCLRAH
VOH
VOL tCHRAL tCLCASH tCLCASH VOH
CAS
VOL
tCHRAV
tCHCAV ROW address VOH VOL VOH VOL tRLDV tCLDV tCADH Read VIH VIL COLUMN address VOH VOL
A24 to A00
VOH VOL
D31 to D16
VIH VIL
DW
VOH VOL tCHDWL tCHDWH
D31 to D16
VOH VOL tCHDV1
Write
VOH VOL
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MB91101/MB91101A
(9) Normal DRAM Mode Fast Page Read/Write Cycle (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time CAS delay time COLUMN address delay time DW delay time Output data delay time CAS valid data input time CAS data hold time Symbol tCLRAH tCLCASL tCLCASH tCHCAV tCHDWH tCHDV1 tCLDV tCADH Pin name CLK, RAS CLK, CAS CLK, CAS CLK, A24 to A00 CLK, DW CLK, D31 to D16 CAS, D31 to D16 CAS, D31 to D16 -- Condition Value Min. -- -- -- -- -- -- -- 0 Max. 6 6 6 15 15 15 tCYC - 17 -- Unit ns ns ns ns ns ns ns ns * Remarks
tCYC (a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing." CAS: CS0L to CS1H pins are for CAS signal outputs. DW: DW0, DW1 and CS0H to CS1H are used for WE outputs. * : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
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MB91101/MB91101A
Q5
Q4 VOH VOL
Q5 VOL
Q4
Q5 VOH VOL
CLK
tCLRAH
RAS
VOH
tCLCASL
tCLCASH VOH
CAS
VOL
tCHCAV
A24 to A00
COLUMN address
VOH VOL
COLUMN address
VOH VOL
COLUMN address
VOH VOL
tCLDV VIH VIL VIH VIL VIH VIL
tCADH VIH VIL VIH VIL VIH VIL
D31 to D16
Read
Read
Read
tCHDWH
DW
VOH
tCHDV1
D31 to D16
VOH VOL
Write
VOH VOL
VOH VOL
Write
VOH VOL
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MB91101/MB91101A
(10) Single DRAM Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time Output data delay time CAS Valid data input time CAS data hold time Symbol tCLRAH2 tCHRAL2 tCHCASL2 tCHCASH2 tCHRAV2 tCHCAV2 tCHDWL2 tCHDWH2 tCHDV2 tCLDV2 tCADH2 Pin name CLK, RAS CLK, RAS CLK, CAS CLK, CAS CLK, A24 to A00 CLK, A24 to A00 CLK, DW CLK, DW CLK, D31 to D16 CAS, D31 to D16 CLK, D31 to D16 -- -- -- -- -- 0 15 15 15 (1 - n/2) x tCYC - 17 -- ns ns ns ns ns -- -- -- -- Condition Value Min. -- Max. 6 6 n/2 x tCYC 6 15 15 Unit ns ns ns ns ns ns Remarks
tCYC (a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."
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MB91101/MB91101A
tCYC Q1 CLK VOH VOL Q2 Q3 VOH
*1 Q4S VOH Q4S VOH Q4S VOH
RAS
VOH tCLRAH2
VOL tCHRAL2 tCHCASL2 tCHCASH2
CAS
VOL
VOH
VOL
VOH
A24 to A00
VOH VOL
ROW address
VOH VOL
VOH VOL COLUMN-0 tCHCAV2
COLUMN-1
COLUMN-2
tCHRAV2
tCADH2 tCLDV2 D31 to D16 Read-0 VIH VIL Read-1 VIH VIL Read-2
DW VOL tCHDWL2
VOH tCHDWH2
D31 to D16
VOH VOL tCHDV2
Write-0
*2 VOH VOL tCHDV2
VOH VOL
VOH VOH VOL VOL Write-1
Write-2
*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high spead page mode.
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MB91101/MB91101A
(11) Hyper DRAM Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time CAS delay time ROW address delay time COLUMN address delay time RD delay time Symbol tCLRAH3 tCHRAL3 tCHCASL3 tCHCASH3 tCHRAV3 tCHCAV3 tCHRL3 tCHRH3 tCLRL3 DW delay time Output data delay time CAS valid data input time CAS data hold time tCHDWL3 tCHDWH3 tCHDV3 tCLDV3 tCADH3 Pin name CLK, RAS CLK, RAS CLK, CAS CLK, CAS CLK, A24 to A00 CLK, A24 to A00 CLK, RD CLK, RD CLK, RD CLK, DW CLK, DW CLK, D31 to D16 CAS, D31 to D16 CLK, D31 to D16 -- Condition Value Min. -- -- -- -- -- -- -- -- -- -- -- -- -- 0 Max. 6 6 n/2 x tCYC 6 15 15 15 15 15 15 15 15 tCYC - 17 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
tCYC (a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."
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MB91101/MB91101A
tCYC Q1 CLK VOH VOL Q2 Q3 VOH
*1 Q4H VOH VOL Q4H VOH Q4H VOH
RAS
VOH tCLRAH3
VOL tCHRAL3 tCHCASL3 tCHCASH3
CAS
VOL
VOH
VOL
VOL
A24 to A00
VOH VOL
ROW address tCHCAV3
VOH VOL
VOHCOLUMN-0 VOL
COLUMN-1
COLUMN-2
tCHRAV3
RD VOL tCHRL3
*2 VOL tCLRL3 tCLDV3
VOH tCHRH3 tCADH3 Read-0 VIH VIL Read-1 VIH VIL
D31 to D16
DW VOL tCHDWL3
VOH tCHDWH3
D31 to D16
VOH VOL tCHDV3
Write-0
*2 VOH VOL tCHDV3
VOH VOL
VOH VOH VOL VOL Write-1
Write-2
*1: Q4H indicates Q4HR (Read) of Single DRAM cycle or Q4HW (Write) cycle. *2: indicates the timing when the bus cycle begins from the high spead page mode.
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MB91101/MB91101A
(12) CBR Refresh (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time CAS delay time Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin name CLK, RAS CLK, RAS CLK, CAS CLK, CAS -- Condition Value Min. -- -- -- -- Max. 6 6 6 6 Unit ns ns ns ns Remarks
CAS: CS0L to CS1H pins are for CAS signal outputs.
tCYC R1
R2 VOH VOL VOH
R3
R4 VOL
CLK
VOH
VOL
RAS
VOH tCLRAH
VOL tCHRAL
CAS
VOL tCLCASL
VOH tCLCASH
DW
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MB91101/MB91101A
(13) Self Refresh (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter RAS delay time CAS delay time Symbol tCLRAH tCHRAL tCLCASL tCLCASH Pin name CLK, RAS CLK, RAS CLK, CAS CLK, CAS -- Condition Value Min. -- -- -- -- Max. 6 6 6 6 Unit ns ns ns ns Remarks
CAS: CS0L to CS1H pins are for CAS signal outputs.
tCYC SR1
SR2 VOH VOL VOH
SR3
SR3 VOL
CLK
VOH
tCHRAL
tCLRAH VOH
RAS
VOL
CAS
VOL tCLCASL
VOH tCLCASH
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MB91101/MB91101A
(14) UART Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Serial clock cycle time SCLK SCLK SCLK SCLK Valid SIN SCLK SCLK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width Valid SIN SCLK SCLK valid SIN hold time Symbol Pin name Condition tSCYC tSCLCH tSCHCL -- -- -- -- -- -- -- -- External shift clock mode tIVSH tSHIX tSHSL tSLSH tIVSH tSHIX Internal shift clock mode -- Value Min. 8 x tCYCP Max. -- Unit ns ns ns ns ns ns ns ns ns ns ns Remarks
4 x tCYCP -10 4 x tCYCP +10 4 x tCYCP -10 4 x tCYCP +10 -80 100 60 4 x tCYCP 4 x tCYCP -- 60 60 80 -- -- -- -- 150 -- --
SCLK SOUT delay time tSLOV
SCLK SOUT delay time tSLOV
tCYCP: A cycle time of peripheral system clock Notes: This rating is for AC characteristics in CLK synchronous mode. * Internal shift clock mode
tSCYC tSCLCH tSCHCL VOH VOL tSLOV VOH VOL tIVSH tSHIX VIH VIL VOL
SCLK
SOUT
SIN
VIH VIL
* External shift clock mode
tSLSH tSHSL VIH VIL tSLOV VOH VOL tIVSH tSHIX VIH VIL VIL VIH
SCLK
SOUT
SIN
VIH VIL
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MB91101/MB91101A
(15) Trigger System Input Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter A/D start trigger input time Symbol tTRGH, tTRGL Pin name ATG -- TRG0 to TRG3 5 x tCYCP -- ns Condition Value Min. 5 x tCYCP Max. -- Unit ns Remarks
PWM external trigger input tTRGH, tTRGL time
tCYCP: A cycle time of peripheral system clock
tTRGH
tTRGL VIH VIL VIL
ATG TRG0 to TRG3
VIH
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(16) DMA Controller Timing (VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = 0C to +70C) (VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0C to +70C) Parameter Symbol Pin name DREQ0 to DREQ2 CLK, DACK0 to DACK2 CLK, DACK0 to DACK2 CLK, EOP0 to EOP2 CLK, EOP0 to EOP2 CLK, DACK0 to DACK2 CLK, DACK0 to DACK2 CLK, EOP0 to EOP2 CLK, EOP0 to EOP2 -- Condition Value Min. 2 x tCYC -- -- -- -- -- -- -- -- Max. -- 6 6 6 6 n/2 x tCYC 6 n/2 x tCYC 6 Unit ns ns ns ns ns ns ns ns ns Remarks
DREQ input pulse width tDRWH DACK delay time (Normal bus) (Normal DRAM) EOP delay time (Normal bus) (Normal DRAM) DACK delay time (Single DRAM) (Hyper DRAM) EOP delay time (Single DRAM) (Hyper DRAM) tCLDL tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH
tCYC (a cycle time of peripheral system clock): Refer to "(2) Clock Output Timing."
tCYC
CLK
VOH
VOL
VOH
VOL
DACK0 to DACK2 EOP0 to EOP2 (Normal bus) (Normal DRAM) DACK0 to DACK2 EOP0 to EOP2 (Single DRAM) (Hyper DRAM)
tCHDL tCHEL
tCLDL tCLEL VOL VOH
tCLDH tCLEH
VOL
VOH
tCHDH
tDRWH
DREQ0 to DREQ2
VIH
VIH
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5. A/D Converter Block Electrical Characteristics
(AVCC = 2.7 V to 3.6 V, AVSS = 0.0 V, AVRH = 2.7 V, TA = 0C to +70C) Parameter Resolution Total error Linearity error Differentiation linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Conversion variance between channels IA IAH IR IRH -- Symbol -- -- -- -- VOT VFST -- IAIN VAIN -- Pin name -- -- -- -- AN0 to AN3 -- AN0 to AN3 AN0 to AN3 AVRH AVCC AVCC AVRH AVRH AN0 to AN3 Value Min. -- -- -- -- -1.5 5.6 *1 -- AVSS AVSS -- -- -- -- -- Typ. 10 -- -- -- +0.5 -- 0.1 -- -- 4 -- 200 -- -- Max. 10 4.0 3.5 2.0 +2.5 -- 10 AVRH AVCC -- 5* 5* 4
2
Unit bit LSB LSB LSB LSB s A V V mA A A A LSB
AN0 to AN3 AVRH - 4.5 AVRH - 1.5 AVRH + 0.5 LSB
--
2
*1: AVCC = 2.7 V - 3.6 V *2: Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.6 V) Notes: * As the absolute value of AVRH decreases, relative error increases. * Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 10 k. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling (sampling time is 5.6 s for a machine clock of 25 MHz). * Analog input circuit model plan
Sample and hold circuit Analog input C0 Comparator RON1 RON1 : 0.2 k RON2 : 1.4 k RON3 : 1.4 k RON4 : 0.2 k RON2 RON3 RON4 C1
C0 : 16.6 pF C1 : 4.0 pF
Note: Listed values are for reference purposes only.
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6. A/D Converter Glossary
* Resolution The smallest change in analog voltage detected by A/D converter. * Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000 0000" "00 0000 0001") to the full-scale transition point (between "11 1111 1110" "11 1111 1111"). * Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage.
Linearity error 3FF 3FE {1 LSB x (N - 1) + VOT} 3FD Digital output VFST (measured value) 004 003 002 Ideal characteristic 001 VOT (measured value) AVRL Analog input AVRH AVRL Analog input N-2 Actual conversion characteristic AVRH VNT (measured value) Actual conversion characteristic Digital output N Differential linearity error
Actual conversion characteristic N+1 Actual characteristic
Ideal characteristic
N-1 V(N + 1)T VNT (measured value) (measured value)
Linearity error of digital output N =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB
[LSB]
Differential linearity error of digital output N =
V(N + 1)T - VNT 1 LSB - 1 [LSB]
1 LSB =
VFST - VOT 1022
[V]
VOT: A voltage for causing transition of digital output from (000)H to (001)H VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H VNT: A voltage for causing transition of digital output from (N - 1)H to N
(Continued)
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(Continued) * Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error 3FF 1.5 LSB' 3FE Actual conversion characteristic 3FD Digital output {1 LSB' x (N - 1) + 0.5 LSB'}
004 003 002 001 VNT (measured value) Actual conversion characteristic Ideal characteristic
0.5 LSB' AVRL Analog input AVRH
Total error of digital output N =
VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB'
[LSB]
1 LSB' (ideal value) = VOT'
AVRH - AVRL 1024
[V]
(ideal value) = AVRL + 0.5 LSB' [V]
VFST' (ideal value) = AVRL - 1.5 LSB' [V] VNT: A voltage for causing transition of digital output from (N - 1) to N
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MB91101/MB91101A
s REFERENCE DATA
1. Operating frequency vs. ICC characteristics
Internal DC - DC regulator is not used (VCC = 3 V) ICC (mA) 90 (VCC) 80 70 60 50 40 30 20 10 0 0 10 f (MHz) 20 30 40 50 3.3 V 3.0 V 2.7 V 40 30 20 10 0 0 10 f (MHz) 20 30 40 50 3.6 V 80 4.5 V to 5.5 V 70 60 50 90 (VCC) Internal DC - DC regulator is used (VCC = 5 V) ICC (mA)
Operating conditions : Source oscillation 12.5 MHz (crystal), PLL is used (50 M, 25 M, 12.5 M) Gear : CPU = 1/1, Peripherals = 1/1 (Doubler is used for 50MHz, Gear peripherals = 1/2)
2. VCC vs. ICC characteristics
Internal DC - DC regulator is not used (VCC = 3 V) Icc (mA) 18 Gear : 1/1 16 14 Gear : 1/2 12 14 Gear : 1/4 10 Gear : 1/8 8 4 2 0 VCC (V) 2.7 3.0 3.3 3.6 Gear : 1/8 (PLL : off) 8 4 2 0 10 12 16 18
Internal DC - DC regulator is used (VCC = 5 V) ICC (mA)
Gear : 1/1 14 Gear : 1/2 14 Gear : 1/4 Gear : 1/8 Gear : 1/8 (PLL : off) 4.5 5.0 5.5
VCC (V)
Operating conditions : Source oscillation 12.5 MHz (crystal), divide-by-2 input, PLL : ON Gear : CPU = Peripherals
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MB91101/MB91101A
s INSTRUCTIONS (165 INSTRUCTIONS)
1. How to Read Instruction Set Summary
Mnemonic ADD * ADD Rj, Ri #s5, Ri , , (2) Type A C , , (3) OP A6 A4 , , (4) CYC 1 1 , , (5) NZVC CCCC CCCC , , (6) Operation Ri + Rj Ri Ri + s5 Ri , , (7) Remarks
(1)
(1) Names of instructions Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels. (2) Addressing modes specified as operands are listed in symbols. Refer to "2. Addressing mode symbols" for further information. (3) Instruction types (4) Hexa-decimal expressions of instructions (5) The number of machine cycles needed for execution a: Memory access cycle and it has possibility of delay by Ready function. b: Memory access cycle and it has possibility of delay by Ready function. If an object register in a LD operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or if the instruction belongs to instruction format A group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. For a, b, c and d, minimum execution cycle is 1. (6) Change in flag sign * Flag change C : Change - : No change 0 : Clear 1 : Set * Flag meanings N : Negative flag Z : Zero flag V : Over flag C : Carry flag (7) Operation carried out by instruction
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2. Addressing Mode Symbols
Ri Rj R13 Ps Rs CRi CRj #i8 : Register direct (R0 to R15, AC, FP SP) , : Register direct (R0 to R15, AC, FP SP) , : Register direct (R13, AC) : Register direct (Program status register) : Register direct (TBR, RP SSP USP MDH, MDL) , , , : Register direct (CR0 to CR15) : Register direct (CR0 to CR15) : Unsigned 8-bit immediate (-128 to 255) Note: -128 to -1 are interpreted as 128 to 255 #i20 : Unsigned 20-bit immediate (-0X80000 to 0XFFFFF) Note: -0X7FFFF to -1 are interpreted as 0X7FFFF to 0XFFFFF #i32 : Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: -0X80000000 to -1 are interpreted as 0X80000000 to 0XFFFFFFFF #s5 : Signed 5-bit immediate (-16 to 15) #s10 : Signed 10-bit immediate (-512 to 508, multiple of 4 only) #u4 : Unsigned 4-bit immediate (0 to 15) #u5 : Unsigned 5-bit immediate (0 to 31) #u8 : Unsigned 8-bit immediate (0 to 255) #u10 : Unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : Unsigned 8-bit direct address (0 to 0XFF) @dir9 : Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only) @dir10 : Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only) label9 : Signed 9-bit branch address (-0X100 to 0XFC, multiple of 2 only) label12 : Signed 12-bit branch address (-0X800 to 0X7FC, multiple of 2 only) label20 : Signed 20-bit branch address (-0X80000 to 0X7FFFF) label32 : Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF) @Ri : Register indirect (R0 to R15, AC, FP SP) , @Rj : Register indirect (R0 to R15, AC, FP SP) , @(R13, Rj) : Register relative indirect (Rj: R0 to R15, AC, FP SP) , @(R14, disp10) : Register relative indirect (disp10: -0X200 to 0X1FC, multiple of 4 only) @(R14, disp9) : Register relative indirect (disp9: -0X100 to 0XFE, multiple of 2 only) @(R14, disp8) : Register relative indirect (disp8: -0X80 to 0X7F) @(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only) @Ri+ : Register indirect with post-increment (R0 to R15, AC, FP SP) , @R13+ : Register indirect with post-increment (R13, AC) @SP+ : Stack pop @-SP : Stack push (reglist) : Register list
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MB91101/MB91101A
3. Instruction Types
MSB 16 bits OP 8 Rj 4 Ri 4 LSB
Type A
Type B
OP 4
i8/o8 8
Ri 4
Type C
OP 8
u4/m4 4
Ri 4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only Type *C' OP 7 s5/u5 5 Ri 4
Type D
OP 8
u8/rel8/dir/reglist 8
Type E
OP 8
SUB-OP 4
Ri 4
Type F
OP 5
rel11 11
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4. Detailed Description of Instructions
* Add/subtract operation instructions (10 instructions) Mnemonic ADD * ADD ADD ADD2 ADDC ADDN * ADDN ADDN ADDN2 SUB SUBC SUBN Rj, Ri #s5, Ri #i4, Ri #i4, Ri Rj, Ri Rj, Ri #s5, Ri #i4, Ri #i4, Ri Rj, Ri Rj, Ri Rj, Ri
Type
OP A6 A4 A4 A5 A7 A2 A0 A0 A1 AC AD AE
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1
Operation
Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension Add operation with sign MSB is interpreted as a sign in assembly language Zero-extension Sign-extension
A C' C C A A C' C C A A A
C C C C Ri + Rj Ri C C C C Ri + s5 Ri C C C C Ri + extu (i4) Ri C C C C Ri + extu (i4) Ri C C C C Ri + Rj + c Ri - - - - Ri + Rj Ri - - - - Ri + s5 Ri - - - - Ri + extu (i4) Ri - - - - Ri + extu (i4) Ri C C C C Ri - Rj Ri C C C C Ri - Rj - c Ri - - - - Ri - Rj Ri
Subtract operation with carry
* Compare operation instructions (3 instructions) Mnemonic CMP * CMP CMP CMP2 Rj, Ri #s5, Ri #i4, Ri #i4, Ri
Type
OP AA A8 A8 A9
Cycle N Z V C 1 1 1 1
Operation
Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension
A C' C C
C C C C Ri - Rj C C C C Ri - s5 C C C C Ri + extu (i4) C C C C Ri + extu (i4)
* Logical operation instructions (12 instructions) Mnemonic AND AND ANDH ANDB OR OR ORH ORB EOR EOR EORH EORB Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri
Type
OP 82 84 85 86 92 94 95 96 9A 9C 9D 9E
Cycle N Z V C 1 1 + 2a 1 + 2a 1 + 2a 1 1 + 2a 1 + 2a 1 + 2a 1 1 + 2a 1 + 2a 1 + 2a CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - - - - - - - - - - - - - Ri & (Ri) & (Ri) & (Ri) & Ri (Ri) (Ri) (Ri) | | | |
Operation = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj
Remarks Word Word Half word Byte Word Word Half word Byte Word Word Half word Byte
A A A A A A A A A A A A
Ri ^ (Ri) ^ (Ri) ^ (Ri) ^
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* Bit manipulation arithmetic instructions (8 instructions) Mnemonic BANDL BANDH * BAND BORL BORH * BOR BEORL BEORH * BEOR BTSTL BTSTH #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH) #u8, @Ri #u4, @Ri (u4: 0 to 0FH) #u4, @Ri (u4: 0 to 0FH)
Type
OP 80 81
Cycle N Z V C
Operation
Remarks Manipulate lower 4 bits Manipulate upper 4 bits
C C *1 C C *2 C C *3 C C
1 + 2a - - - - (Ri) & = (F0H + u4) 1 + 2a - - - - (Ri) & = ((u4<<4) + 0FH) - - - - - (Ri) & = u8
90 91
1 + 2a - - - - (Ri) | = u4 1 + 2a - - - - (Ri) | = (u4<<4) - - - - - (Ri) | = u8
Manipulate lower 4 bits Manipulate upper 4 bits
98 99
1 + 2a - - - - (Ri) ^ = u4 1 + 2a - - - - (Ri) ^ = (u4<<4) - - - - - (Ri) ^ = u8 0 C - - (Ri) & u4 C C - - (Ri) & (u4<<4)
Manipulate lower 4 bits Manipulate upper 4 bits
88 89
2+a 2+a
Test lower 4 bits Test upper 4 bits
*1: Assembler generates BANDL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BANDH if "u8&0xF0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH may be generated. *2: Assembler generates BORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BORH if "u8&0xF0" leaves an active bit. *3: Assembler generates BEORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BEORH if "u8&0xF0" leaves an active bit. * Add/subtract operation instructions (10 instructions) Mnemonic MUL MULU MULH MULUH DIVOS DIVOU DIV1 DIV2 DIV3 DIV4S * DIV * DIVU Rj, Ri Rj, Ri Rj, Ri Rj, Ri Ri Ri Ri Ri Ri Ri *1 *2
Type
OP AF AB BF BB 97 - 4 97 - 5 97 - 6 97 - 7 9F - 6 9F - 7
Cycle N Z V C 5 5 3 3 1 1 d 1 1 1 - - CCC CCC CC- CC- - - - - - - - - - C C - - C - - - - - - - - - - -
Operation Rj x Ri MDH, MDL Rj x Ri MDH, MDL Rj x Ri MDL Rj x Ri MDL
Remarks 32-bit x 32-bit = 64-bit Unsigned 16-bit x 16-bit = 32-bit Unsigned Step calculation 32-bit/32-bit = 32-bit
A A A A E E E E E E
- - C C - - C MDL/Ri MDL, MDL%Ri MDH - C - C MDL/Ri MDL, MDL%Ri MDH
Unsigned
*1: DIVOS, DIV1 x 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes. *2: DIVOU and DIV1 x 32 are generated. A total instruction code length of 66 bytes.
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* Shift arithmetic instructions (9 instructions) Mnemonic LSL * LSL LSL LSL2 LSR * LSR LSR LSR2 ASR * ASR ASR ASR2 Rj, Ri #u5, Ri #u4, Ri #u4, Ri Rj, Ri #u5, Ri #u4, Ri #u4, Ri Rj, Ri #u5, Ri #u4, Ri #u4, Ri
Type
OP B6 B4 B4 B5 B2 B0 B0 B1 BA B8 B8 B9
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - C C C C C C C C C C C C
Operation Ri<>Rj Ri Ri>>u5 Ri Ri>>u4 Ri Ri>>(u4 + 16) Ri Ri>>Rj Ri Ri>>u5 Ri Ri>>u4 Ri Ri>>(u4 + 16) Ri
Remarks Logical shift
A C' C C A C' C C A C' C C
Logical shift
Logical shift
* Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) Mnemonic LDI: 32 LDI: 20 LDI: 8 * LDI #i32, Ri #i20, Ri #i8, Ri # {i8 | i20 | i32}, Ri *1
Type
OP 9F - 8 9B C0
Cycle N Z V C 3 2 1
Operation
Remarks Upper 12 bits are zeroextended Upper 24 bits are zeroextended
E C B
- - - - i32 Ri - - - - i20 Ri - - - - i8 Ri {i8 | i20 | i32} Ri
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. If an immediate value contains relative value or external reference, assembler selects i32. * Memory load instructions (13 instructions) Mnemonic LD LD LD LD LD LD LD LDUH LDUH LDUH LDUB LDUB LDUB @Rj, Ri @(R13, Rj), Ri @(R14, disp10), Ri @(R15, udisp6), Ri @R15 +, Ri @R15 +, Rs @R15 +, PS @Rj, Ri @(R13, Rj), Ri @(R14, disp9), Ri @Rj, Ri @(R13, Rj), Ri @(R14, disp8), Ri
Type
OP 04 00 20 03 07 - 0 07 - 8 07 - 9 05 01 40 06 02 60
Cycle N Z V C b b b b b b
1+a+b
Operation (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + udisp6) Ri (R15) Ri, R15 + = 4 (R15) Rs, R15 + = 4
Remarks
A A B C E E E A A B A A B
- - - - - -
- - - - - -
- - - - - -
- - - - - -
C C C C (R15) PS, R15 + = 4 - - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp9) Ri - - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp8) Ri
Rs: Special-purpose register Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension
b b b b b b
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 o8 = disp8 disp9 o8 = disp9>>1 Each disp is a code extension. disp10 o8 = disp10>>2 udisp6 u4 = udisp6>>2 udisp4 is a 0 extension. 102
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* Memory store instructions (13 instructions) Mnemonic ST ST ST ST ST ST ST STH STH STH STB STB STB Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp10) Ri, @(R15, udisp6) Ri, @-R15 Rs, @-R15 PS, @-R15 Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp9) Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp8)
Type
OP 14 10 30 13 17 - 0 17 - 8 17 - 9 15 11 50 16 12 70
Cycle N Z V C a a a a a a a a a a a a a - - - - - - - - - - - - - - - - - - - - - - - -
Operation Ri (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + usidp6) R15 - = 4, Ri (R15) R15 - = 4, Rs (R15) Word Word Word
Remarks
A A B C E E E A A B A A B
- - - - R15 - = 4, PS (R15) - - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp9) - - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp8)
Rs: Special-purpose register Half word Half word Half word Byte Byte Byte
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 o8 = disp8 disp9 o8 = disp9>>1 Each disp is a code extension. disp10 o8 = disp10>>2 udisp6 u4 = udisp6>>2 udisp4 is a 0 extension. * Transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) Mnemonic MOV MOV MOV MOV MOV Rj, Ri Rs, Ri Ri, Rs PS, Ri Ri, PS
Type
OP 8B B7 B3 17 - 1 07 - 1
Cycle N Z V C 1 1 1 1 c
Operation
Remarks Transfer between general-purpose registers Rs: Special-purpose register Rs: Special-purpose register
A A A E E
- - - - Rj Ri - - - - Rs Ri - - - - Ri Rs - - - - PS Ri C C C C Ri PS
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* Non-delay normal branch instructions (23 instructions) Mnemonic JMP CALL CALL RET INT #u8 @Ri label12 @Ri
Type
OP 97 - 0 D0 97 - 1 97 - 2 1F
Cycle N Z V C 2 2 2 2 3+3a
Operation
Remarks
E F E E D
- - - - Ri PC - - - - PC + 2 RP , PC + 2 + rel11 x 2 PC - - - - PC + 2 RP Ri PC , - - - - RP PC - - - - SSP - = 4, PS (SSP), SSP - = 4, PC + 2 (SSP), 0 I flag, 0 S flag, (TBR + 3FC - u8 x 4) PC Return
INTE
E
9F - 3 3 + 3a - - - - SSP - = 4, PS (SSP), For emulator SSP - = 4, PC + 2 (SSP), 0 S flag, (TBR + 3D8 - u8 x 4) PC 97 - 3 2 + 2a C C C C (R15) PC, R15 - = 4, (R15) PS, R15 - = 4 E1 E0 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Non-branch PC + 2 + rel8 x 2 PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0
RETI BNO BRA BEQ BNE BC BNC BN BP BV BNV BLT BGE BLE BGT BLS BHI label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9
E D D D D D D D D D D D D D D D D
Notes: * "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. * The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 - PC - 2)/2 label12 rel11 = (label12 - PC - 2)/2 * RETI must be operated while S flag = 0.
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MB91101/MB91101A
* Branch instructions with delays (20 instructions) Mnemonic JMP:D CALL:D CALL:D RET:D BNO:D BRA:D BEQ:D BNE:D BC:D BNC:D BN:D BP:D BV:D BNV:D BLT:D BGE:D BLE:D BGT:D BLS:D BHI:D label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 @Ri label12 @Ri
Type
OP 9F - 0 D8 9F - 1 9F - 2 F1 F0 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Operation
Remarks
E F E E D D D D D D D D D D D D D D D D
- - - - Ri PC - - - - PC + 4 RP , PC + 2 + rel11 x 2 PC - - - - PC + 4 RP Ri PC , - - - - RP PC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Non-branch PC + 2 + rel8 x 2 PC PCif Z = = 1 PCif Z = = 0 PCif C = = 1 PCif C = = 0 PCif N = = 1 PCif N = = 0 PCif V = = 1 PCif V = = 0 PCif V xor N = = 1 PCif V xor N = = 0 PCif (V xor N) or Z = = 1 PCif (V xor N) or Z = = 0 PCif C or Z = = 1 PCif C or Z = = 0 Return
Notes: * The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and assembler discription label9 and label12 are as follows. label9 rel8 = (label9 - PC - 2)/2 label12 rel11 = (label12 - PC - 2)/2 * Delayed branch operation always executes next instruction (delay slot) before making a branch. * Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other instruction is stored, this device may operate other operation than defined. The instruction described "1" in the other cycle column than branch instruction. The instruction described "a", "b", "c" or "d" in the cycle column.
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MB91101/MB91101A
* Direct addressing instructions Mnemonic DMOV DMOV DMOV DMOV DMOV DMOV DMOVH DMOVH DMOVH DMOVH DMOVB DMOVB DMOVB DMOVB @dir10, R13, @dir10, @R13+, @dir10, @R15+, @dir9, R13, @dir9, @R13+, @dir8, R13, @dir8, @R13+, R13 @dir10 @R13+ @dir10 @-R15 @dir10 R13 @dir9 @R13+ @dir9 R13 @dir8 @R13+ @dir8
Type
OP 08 18 0C 1C 0B 1B 09 19 0D 1D 0A 1A 0E 1E
Cycle N Z V C b a 2a 2a 2a 2a b a 2a 2a b a 2a 2a - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Operation (dir10) R13 R13 (dir10) (dir10) (R13), R13 + = 4 (R13) (dir10), R13 + = 4 R15 - = 4, (dir10) (R15) (R15) (dir10), R15 + = 4 (dir9) R13 R13 (dir9) (dir9) (R13), R13 + = 2 (R13) (dir9), R13 + = 2 (dir8) R13 R13 (dir8) (dir8) (R13), R13 + + (R13) (dir8), R13 + + Word Word Word Word Word Word
Remarks
D D D D D D D D D D D D D D
Half word Half word Half word Half word Byte Byte Byte Byte
Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 dir + disp8 disp9 dir = disp9>>1 Each disp is a code extension disp10 dir = disp10>>2 * Resource instructions (2 instructions) Mnemonic LDRES STRES @Ri+, #u4, #u4 @Ri+
Type
OP BC BD
Cycle N Z V C a a
Operation
Remarks u4: Channel number u4: Channel number
C C
- - - - (Ri) u4 resource Ri + = 4 - - - - u4 resource (Ri) Ri + = 4
* Co-processor instructions (4 instructions) Mnemonic COPOP COPLD COPST COPSV #u4, #CC, CRj, CRi #u4, #CC, Rj, CRi #u4, #CC, CRj, Ri #u4, #CC, CRj, Ri
Type
OP 9F - C 9F - D 9F - E 9F - F
Cycle N Z V C 2+a 1 + 2a 1 + 2a 1 + 2a - - - - - - - - - - - - - - - -
Operation Calculation Rj CRi CRj Ri CRj Ri
Remarks
E E E E
No error traps
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MB91101/MB91101A
* Other instructions (16 instructions) Mnemonic NOP ANDCCR #u8 ORCCR #u8 STILM ADDSP EXTSB EXTUB EXTSH EXTUH LDM0 LDM1 * LDM STM0 STM1 * STM2 ENTER #u8 #s10 Ri Ri Ri Ri (reglist) (reglist) (reglist) (reglist) (reglist) (reglist) #u10 *5 *2 D 0F *3 D D 8E 8F *1
Type
OP 9F - A 83 93 87 A3 97 - 8 97 - 9 97 - A 97 - B 8C 8D
Cycle N Z V C 1 c c 1 1 1 1 1 1 *4 *4 - *6 *6 - 1+a
Operation
Remarks
E D D D D E E E E D D
- - - - No changes C C C C CCR and u8 CCR C C C C CCR or u8 CCR - - - - i8 ILM - - - - R15 + = s10 - - - - - - - - - - - - - - - - Sign extension 8 32 bits Zero extension 8 32 bits Sign extension 16 32 bits Zero extension 16 32 bits Load-multi R0 to R7 Load-multi R8 to R15 Load-multi R0 to R15 Store-multi R0 to R7 Store-multi R8 to R15 Store-multi R0 to R15 Entrance processing of function Exit processing of function For SEMAFO management Byte data Set ILM immediate value ADD SP instruction
- - - - (R15) reglist, R15 increment - - - - (R15) reglist, R15 increment - - - - (R15 + +) reglist, - - - - R15 decrement, reglist (R15) - - - - R15 decrement, reglist (R15) - - - - reglist (R15 + +) - - - - R14 (R15 - 4), R15 - 4 R14, R15 - u10 R15 - - - - R14 + 4 R15, (R15 - 4) R14 - - - - Ri TEMP , (Rj) Ri, TEMP (Rj)
LEAVE XCHB @Rj, Ri
E A
9F - 9 8A
b 2a
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler description s10 is as follows. s10 s8 = s10>>2 *2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler description u10 is as follows. u10 u8 = u10>>2 *3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified, assembler generates LDM1. Both LDM0 and LDM1 may be generated. *4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following calculation; a x (n - 1) + b + 1 when "n" is number of registers specified. *5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified, assembler generates STM1. Both STM0 and STM1 may be generated. *6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following calculation; a x n + 1 when "n" is number of registers specified.
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MB91101/MB91101A
* 20-bit normal branch macro instructions Mnemonic * CALL20 * BRA20 * BEQ20 * BNE20 * BC20 * BNC20 * BN20 * BP20 * BV20 * BNV20 * BLT20 * BGE20 * BLE20 * BGT20 * BLS20 * BHI20 label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address RP label20 PC , label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL20 (1) If label20 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL @Ri *2: BRA20 (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP @Ri *3: Bcc20 (BEQ20 to BHI20) (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP @Ri false:
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MB91101/MB91101A
* 20-bit delayed branch macro instructions Mnemonic * CALL20:D label20, Ri * BRA20:D * BEQ20:D * BNE20:D * BC20:D * BNC20:D * BN20:D * BP20:D * BV20:D * BNV20:D * BLT20:D * BGE20:D * BLE20:D * BGT20:D * BLS20:D * BHI20:D label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address + 2 RP label20 PC , label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL20:D (1) If label20 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL:D @Ri *2: BRA20:D (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP:D @Ri *3: Bcc20:D (BEQ20:D to BHI20:D) (1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label20 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP:D @Ri false:
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MB91101/MB91101A
* 32-bit normal macro branch instructions Mnemonic * CALL32 * BRA32 * BEQ32 * BNE32 * BC32 * BNC32 * BN32 * BP32 * BV32 * BNV32 * BLT32 * BGE32 * BLE32 * BGT32 * BLS32 * BHI32 label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address RP label32 PC , label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL32 (1) If label32 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL @Ri *2: BRA32 (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP @Ri *3: Bcc32 (BEQ32 to BHI32) (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP @Ri false:
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MB91101/MB91101A
* 32-bit delayed macro branch instructions Mnemonic * CALL32:D label32, Ri * BRA32:D * BEQ32:D * BNE32:D * BC32:D * BNC32:D * BN32:D * BP32:D * BV32:D * BNV32:D * BLT32:D * BGE32:D * BLE32:D * BGT32:D * BLS32:D * BHI32:D label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address + 2 RP label32 PC , label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register Ri: Temporary register *1 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3
*1: CALL32:D (1) If label32 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL:D @Ri *2: BRA32:D (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP:D @Ri *3: Bcc32:D (BEQ32:D to BHI32:D) (1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label32 - PC - 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP:D @Ri false:
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MB91101/MB91101A
s ORDERING INFORMATION
Part number MB91101APFV MB91101APF Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) Remarks
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MB91101/MB91101A
s PACKAGE DIMENSIONS
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 +.002
"A" 0.50(.0197)TYP 0.18 -0.03 .007 -.001
+0.08 +.003
0.40(.016)MAX 0.127 -0.02 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
(Continued)
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MB91101/MB91101A
(Continued)
100-pin Plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
Note: The design may be modified changed without notice, contact to Fujitsu sales division when using the device.
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MB91101/MB91101A
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9907 (c) FUJITSU LIMITED Printed in Japan
115

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